Bruce Querbach

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time

As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software assisted repair technology to automatically repair memory cell defects on 3D stacked Wide-IO DRAM. Additionally, we also present the CPGC gate count, power, simulation, and silicon results. The reusable CPGC IP is designed to connect to a standard IP interface, which enables a quick turn-key SOC development cycle. Silicon results show CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface. CPGC is also used in memory training and initialization, which makes it a critical part of Intel SOC.

Comparison of hardware based and software based stress testing of memory IO interface

In post-silicon testing and validation of circuit functionality, an effective IO stress pattern can identify bugs quickly and provide adequate test coverage. A lot of work has been done to identify the right stress patterns specific to each IO interface. While some patterns can be generic enough to apply to all IOs, other patterns are interface topology specific. In addition to identifying the worst-case pattern, tradeoffs between test-time and test coverage must be made depending on the test goals. Pseudo Random Bit Stream (PRBS) generators are commonly used to generate test patterns because of the adequate frequency content in the PRBS patterns, the ease of implementation, and minimal gate count. This paper introduces an Advanced Pattern Generator and Checker (APGC) based on PRBS that retains all the aforementioned advantages. The APGC was implemented for a DDR memory interface where different LFSRs beat against each other spatially on neighboring IO lanes while rotating this form of aggressor-victim pattern in time. The results of the APGC stress patterns are compared to a form of advanced software-based learning algorithm based patterns that exhaustively search this complete parameter space. The comparison of APGC to software showed that the measured bit error rate (BER) plotted on a Q-scale of both methods is similar for the Receiver side. On the Transmitter side, APGC showed less eye opening than the software. In addition to the margin comparison, on the test execution side, APGC can speed up the test and validation execution time compared to the software by 32 to 2048 times depending on aggressor victim lane width of 8 to 64 lanes.

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

This paper presents the hardware and software architecture of a reusable BIST engine for 3D stacked 14-nm SoC, which also includes software-assisted autorepair of memory defects. Silicon results presented demonstrate the features of such engine such as easy silicon debug, validation time reduction by 3x, detection and repair of memory cell defects, etc. This solution has been successfully designed and used for seven Intel SoCs successfully debugged, tested, and launched into the market place.

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine

As the memory industry pushes to increase memory density, device variation is creating more defects. Furthermore, new form factors (phone, tablet, mobile and client PC) and low cost board and platform limits physical access to JTAG or TAP. Taking advantage of the x86 architectures high functional bandwidth to memory, the quickest way to access and test memory is through CPU core, by storing and running parallel CPGC/BIST test content via CPU L3 cache, one CPGC BIST engine per memory channel. We propose a cache based testing framework that speeds up test time 60× to 170× compared to JTAG or TAP based testing using the same test content. We will present the cache based test (CBT) architecture and infrastructure (MRC/NEM setup, CPGC/IBIST), test content, results, and a side by side comparison of test time to JTAG or TAP. Finally we will discuss and compare this approach to generalized cache based tests.