Jay J. Nejedlo

A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization

A fully-integrated, 3-5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Transmitter pre-emphasis equalization is utilized to mitigate the effect of multipath on bit-error rate (BER). Occupying 2 mm2 die area, the transceiver achieves a data rate of 500 Mbps, energy efficiency of 0.18 nj/b at 500 Mbps, and a RX raw BER of <; 10-3 across a distance of 10 cm at 125 Mbps. In a real multipath environment, BER improves by 2.35× after equalization of the first multipath reflection.

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges

This article advocates the use of short-range wireless communication inside a computing chassis. Ultrawideband links make it possible to design a within-chassis wireless interconnect. In contrast to conventional, fixed, wireline connections between chips, wireless communications offer certain unique advantages, as the authors explain.

Intel ® IBIST, the full vision realized

Third generation Intel® IBIST (IBIST) is the first full featured edition of what was originally envisioned in 1999. The objective was to create a standard infrastructure for validating, debugging, and testing high speed IOs (Input/Output) which could be supported by a common software toolset. This vision was realized in 2009 on Intel products. The IBIST methodology has become a standard at Intel. Today, IBIST is utilized from the very beginning of the product verification including initial power-on silicon debug. It a staple throughout the back-end product validation process and is also utilized in end-customer validation and high volume testing. Intels platform Reliability, Availability, Serviceability(collectively referred to as RAS) architecture exploits the technology on a number of fronts as well. The content of this paper includes an overview of the problems which mandated this paradigm shift away from the historical IO testing methodologies, an IBIST architectural overview, and the key application spaces addressed by this technology.

A 90nm-CMOS, 500Mbps, fully-integrated IR-UWB transceiver using pulse injection-locking for receiver phase synchronization

A fully-integrated, 3.1–5GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR). Occupying 2mm2 die area, the transceiver achieves a maximum data rate of 500 Mbps, energy efficiency of 0.18nJ/b at 500Mbps, and a RX-BER of 10−3 across a distance of 10cm at 125Mbps.

IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

This paper summarizes the test challenges associated with next -generation platform buses and introduces an Intel-developed technology called IBISTTM (Interconnect Built-In Self-Test) created to meet those challenges. The IBISTTM testing methodology and associated on-die architecture customized for PCI Express (PCIe) interface is described.

Understanding the Ultrawideband Channel Characteristics Within a Computer Chassis

A measurement-based, statistical ultrawideband (UWB) channel model is presented for the unique environment within a computer chassis. The channel impulse response parameters are derived from measurement data. Because of the short-range communications, a mixture of near-field and far-field propagation is characterized by the use of a breakpoint path-loss model. Due to the near-field nature of this environment, an unusually large number of clusters and rapid cluster decay time is noted in the channel impulse response. Additionally, electromagnetic interference measured inside a computer chassis that is generated by the motherboard in a custom fully operational mode is presented, wherein it is observed that the CPU clock does not appear as a significant interference source.

IBIST/spl trade/ (interconnect built-in-self-test) architecture and methodology for PCI Express

This paper summarizes the test challenges associated with next generation platform buses and introduces an Intel developed technology called IBIST/spl trade/ created to meet those challenges. The IBIST/spl trade/ testing methodology and associated on-die architecture customized for the PCI Express (PCIe) interface are described.

Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband(IR-UWB) transceivers

This paper presents a novel CMOS 2-tap equalizer for combating multipath interference in impulse radio, ultra-wideband (IR-UWB) transceiver systems. The equalizer is composed of pulse width control, pulse tap delay control, pulse sign inversion, and current mode logic (CML) summation for data transmission. SpectreRF post-layout simulation in a 90-nm CMOS technology shows that the transceiver operates up to a 2Gbps data rate by removing the 1st and 2nd multipath reflections, illustrating significant signal-to-noise (SNR) improvement when compared with a conventional transmitter.

Measurement and characterization of ultra-wideband wireless interconnects within active computing systems

This paper presents experimental measurements of ultra-wideband (UWB) wireless interconnects within an operational computer system chassis. Using an impulse-radio ultra-wideband (IR-UWB) 3–5GHz transceiver, this paper analyzes and verifies the implementation of high-bandwidth wireless communications within an enclosed, heavy multipath, metallic environment such as a computer server chassis. Bit-error-rate (BER) and recovered clock jitter were measured at various positions within the computer chassis. The results show a 6X improvement in BER after applying the equalizer to the noisy channel while the motherboard is fully operating.

Tribute board and platform test methodology: intel's next generation test and validation methodology for platforms

Abstract Built-in self-test (BIST) has been historically silicon-centric in its application. This paper offers an overview of Intel’s next-generation platform test methodology, TRIBuTETM. TRIBuTETM is an Intel-coined acronym for Three-Reuseable-Integrated-Bist-u-TEchnologies. The TRIBuTETM approach targets the replacement of today’s standard platform testing process and exploits BIST in a novel way.... comprehensive board and platform testing.