Bruno Albertini

A computational reflection mechanism to support platform debugging in SystemC

System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity of electronics systems design, where complex SoCs composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper proposes a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform simulation models written in SystemC TLM. This allows them to monitor and change signals or even IP internal register values, thus injecting specific stimuli that guide the simulation flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumentation from the IP designer, do not need a specialized SystemC library, and not even need the IP source code to be able to inspect its contents. The reflection mechanism was implemented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation

The new design challenges imposed by the increasing difficulties of todays electronic systems obligated designers to develop new methodologies. System-level design and platform-based design are playing an important rule in the electronics industry, and design reuse is a key concept. SystemC is a design language which is being largely adopted to raise the abstraction level of hardware design and verification, becoming an important system design language nowadays. Considering the large amount of VHDL RTL modules already available and that systems design are hardly ever started from scratch, co-simulating VHDL and SystemC hardware modules becomes very desirable. This paper presents a new methodology, based on an open-source toolset (libraries and programs), to co-simulate SystemC and VHDL components. We use a platform case study to measure simulation performance and compare our infrastructure to Modelsim.

A novel verification technique to uncover out-of-order DUV behaviors

Post-partitioning verification has to deal with abstract data, implementation artifacts, and the order of events may not be preserved in the DUV due to the concurrency treatment in the golden model. Existing techniques are limited either by the use of greedy heuristics (jeopardizing verification guarantees) or by black-box approaches (impairing observability). This work proposes a novel white-box technique that overcomes those limitations by casting the problem as an extended bipartite graph matching. By relying on proven properties, solid verification guarantees are provided. Experimental validation was performed upon platforms built around contemporary real-life applications.

A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation

Transactional memory (TM) is an emerging synchronization mechanism that aims to solve most of the difficulties inherent in lock-based approaches. TM implementations may either rely on special hardware (HTM) or employ a software-only (STM) technique. While STM can be implemented and evaluated in current machines, HTM requires hardware modification and a prototyping infrastructure. We present in this paper a flexible platform framework for rapid prototyping and evaluation of HTM systems. Platform components such as cache, memory and interconnection medium are implemented using SystemC and transaction-level modeling (TLM). Processors are described in an architecture description language (ADL) which makes it practical to change the instruction set architecture (ISA), since simulators and binary utilities are automatically generated by the ADL toolset. The resulting flexibility allows designers to explore the design space in a simple and uniform manner. We illustrate the platform through a case study based on the original HTM proposed by Herlihy and Moss. Simulation results are shown for mi- crobenchmarks supporting up to 256 processors.

Transaction Level Modeling

The rise of SoCs caused a paradigm shift on system design flow. The TLM methodology was created in the search for a new paradigm that could allow design representation at an intermediate level of abstraction between paper specification and RTL models. This chapter introduces the Transaction Level Modeling (TLM) design methodology. Its main goals are to explain the main concepts behind TLM and to show that it can work very well in SystemC-based designs. That is why we discuss the strong relation between SystemC and TLM and emphasize the main features in the recently released SystemC TLM 2.0 standard. As in Chap. 2, the intention is not to serve as a substitute for the reference manual. Instead, our focus is to provide a good understanting on the underlying ideas and to show how to put TLM to work in SystemC-based platform designs. We finalize this chapter with a simple platform example using the SystemC TLM standard. Following chapters will present more elaborate platform examples by relying on the main concepts and elements introduced in the first part of the book.

Computational reflection and its application to platform verification

The complexity of modern hardware design has created the need for higher levels of abstraction, where system modeling is used to integrate modules into complex System-on-Chip (SoCs) platforms. SystemC, and its TLM (Transaction Level Modeling) extensions, have been used for this purpose mainly because of their fast prototyping and simulation features, which allow for early design space exploration. This paper proposes an approach to explore and interact with SystemC models by means of an introspection technique known as Computational Reflection. We use reflection to implement a white-box introspection mechanism called ReflexBox. We show that ReflexBox is a fast, non-intrusive technique that can be used to dynamically gather and inject stimuli into any SystemC module, without the need to use a proprietary SystemC implementation, change the SystemC library, instrument or even inspect the module source code. Our approach can be used to support many different verification tasks like platform debugging, performance evaluation and communication analysis. To show ReflexBox effectiveness we used it in three platforms case studies to address tasks like register inspection, performance analysis and signal replaying for testbench reuse. In all cases we assumed no source code availability and measured the impact on the overall platform performance.

Building Platform Models with SystemC

This chapter will guide you through the process of designing a virtual platform. We start with a very simple Hello World example and expand it to a dual-core platform to serve as a basis for a MP3 decoder platform that is explained and implemented in the second part of the chapter. The MP3 decoder design starts with a profilling as the basis for a hardware-software partition, which guided us to create two IPs and integrated them to the rest of the software. At the end of the chapter, we discuss how the software could be partitioned to cope with the designed platform.

Debugging SystemC Platform Models

In the Electronic System Level (ESL) environment, a key factor is the early integration of verification into the design flow. Higher levels of abstraction must not be appealing just for their fast simulation speeds, but also for their flexibility and capabilities when debug and analysis come into play. This creates a demand for new functionalities related to verification in TLM platform models and/or simulation environments. In this chapter, We discuss a mechanism that relies on computational reflection to enable designers to interact with the platform simulation on the fly. This allows them to monitor and change signals or IP internal register values at runtime, so as to explore in high level of details what is happening within each platform module.