Cristiano C. de Araujo

The ArchC architecture description language and tools

This paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemC-based language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and co-verification interfaces. ArchC’s key features are a storage-based co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators and assemblers. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS and Intel 8051 processors, as well as functional models of architectures like SPARC V8, TMS320C62x, XScale and PowerPC.

Hyperspectral images clustering on reconfigurable hardware using the k-means algorithm

Unsupervised clustering is a powerful technique for understanding multispectral and hyperspectral images, k-means being one of the most used iterative approaches. It is a simple though computationally expensive algorithm, particularly for clustering large hyperspectral images into many categories. Software implementation presents advantages such as flexibility and low cost for implementation of complex functions. However, it presents limitations, such as difficulties in exploiting parallelism for high performance applications. In order to accelerate the k-means clustering, a hardware implementation could be used. The disadvantage in this approach is that any change in the project requires previous knowledge of the hardware design process and can take several weeks to be implemented. In order to improve the design methodology, an automatic and parameterized implementation for hyperspectral images has been developed in a hardware/software codesign approach. An unsupervised clustering technique k-means that uses the Euclidian distance to calculate the pixel to centers distance was used as a case study to validate the methodology. Two implementations, a software and a hardware/software codesign one, have been implemented. Although the hardware component operates at 40 MHz, being 12.5 times less than the software operating frequency (PC), the codesign implementation was approximately 2 times faster than software one.

A computational reflection mechanism to support platform debugging in SystemC

System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity of electronics systems design, where complex SoCs composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper proposes a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform simulation models written in SystemC TLM. This allows them to monitor and change signals or even IP internal register values, thus injecting specific stimuli that guide the simulation flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumentation from the IP designer, do not need a specialized SystemC library, and not even need the IP source code to be able to inspect its contents. The reflection mechanism was implemented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.

An ESL approach for energy consumption analysis of cache memories in SoC platforms

The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an architecture that meets performance and power consumption requirements. Thus, developing new high-level specification mechanisms for the reduction of the design effort with automatic architecture exploration is a necessity. This paper proposes an Electronic-System-Level (ESL) approach for system modeling and cache energy consumption analysis of SoCs called PCacheEnergy Analyzer. It uses as entry a high-level UML-2.0 profile model of the system and it generates a simulation model of a multicore platform that can be analyzed for cache tuning. PCacheEnergyAnalyzer performs static/dynamic energy consumption analysis of caches on platforms that may have different processors. Architecture exploration is achieved by letting designers choose different processors for platform generation and different mechanisms for cache optimization. PCacheEnergy Analyzer has been validated with several applications of Mibench, Mediabench, and PowerStone benchmarks, and results show that it provides analysis with reduced simulation effort

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.

Building a Quality Mobile Application: A User-Centered Study Focusing on Design Thinking, User Experience and Usability

This article describes the creation of a mobile application through Design Thinking (DT), User Experience (UX) and usability guidelines approach in the undergraduate setting. The aim of this paper is to present the whole creative process involved in designing a mobile application, within the ideology of Design Thinking, which offers a comprehensive, reliable and, above all, simple experience. The app was built by a team of inexperienced undergraduate students in Computer Science, Computer Engineering and Design at the Federal University of Pernambuco, during a process that lasted a month. As a result, the application has obtained a high success rate, being the third most downloaded application of all genres in the first week it became available in BlackBerry Store, and also getting extremely high ratings by leading technology websites in Brazil.

Software Project Management Combining Agile, Lean Startup and Design Thinking

This paper describes a project management model named Converge, that combines Agile, Lean Startup and Design Thinking with the aim of producing user-centered software and sustainable innovation through empathy with users. The model is based on previous works combining the aforementioned methodologies and adjusted considering needs that arose from teams inside the lab, observed empirically. In order to test the method’s validity in a real project, an undergraduate team part of an experimentation lab followed the proposed model to guide the development of a homonymous data storage app.

An environment for energy consumption analysis of cache memories in SoC platforms

The tuning of cache architectures in platforms for embedded systems applications can dramatically reduce energy consumption. The existing cache exploration environments constrain the designer to analyze cache energy consumption on single processor systems and worse, systems that are based on a single processor type. In this paper is presented the PCacheEnergyAnalyzer environment for energy consumption analysis of cache memory on SoC platforms. This is a powerful energy analysis environment that combines the use of efficient tools to provide static and dynamic energy consumption analysis, the flexibility to support the architecture exploration of cache memories on platforms that are not bound to a specific processor, and fast simulation techniques. The proposed environment has been integrated into the SoC modeling framework PDesigner, providing a user-friendly graphical interface allowing the integrated modeling and cache energy analysis of SoCs. The PCacheEnergyAnalyzer has been validated with four applications of the Mediabench suite benchmark.

Interface generation for concurrent processes during hardware/software co-synthesis

This paper describes an interface model, which is being used in the PISH co-design system. This model is based on layers, and tries to keep the interface generation as independent as possible of the underlying target architecture. The proposed interface structuring, in three layers, provides abstraction of the communication implementation at process level and makes the interface generation process easier.

Pet Empires: Combining Design Thinking, Lean Startup and Agile to Learn from Failure and Develop a Successful Game in an Undergraduate Environment

Startups are able to produce software products with a strong impact on the market, significantly contribution to the global economy. However, eight of ten software startups fail within their first three years - the main failure is caused by the high cost of getting the first customer and the even higher cost of getting the product wrong. In order to reduce these failures, more recent research has focused on combining the approaches of Design Thinking (DT), Lean Startup and Agile to develop and scale new products. This research aims to offer new insights on how startups can benefit by combing the approaches above to developing new software products. As a result, this paper provides a model which demonstrated good potential to be used by startups.