Bryan D. Ackland

A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PEs) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

Camera on a chip

Recent advances in video compression and digital networking technology, combined with the ever increasing power of PCs and workstations, are creating enormous opportunities to develop new multimedia products and services built upon sophisticated voice, data, image and video processing. This will create a significant demand for compact, low-cost, low-power electronic cameras for video and still image capture. These cameras will be a standard peripheral on all PCs bundled for multimedia applications. Given that in excess of 60M PCs will be sold this year, a sizable new market for electronic cameras is being created.

A 256/spl times/256 CMOS active pixel image sensor with motion detection

This 256/spl times/256 active pixel sensor (APS) is designed for consumer multimedia applications requiring low-cost, high-functionality, compact cameras capable of acquiring high-quality images at video frame rates. This sensor allows random access of the image data, permitting a simple implementation of electronic pan and zoom. Use in portable equipment is simplified by standard operating voltages and low power (80mW@5V, 20mW@3.3V). Fabrication in a standard CMOS process allows the integration of a variety of new and existing digital circuits with the image sensor. In addition, by making use of the implicit dynamic frame buffer provided by the active pixel structure, the sensor can generate a signal that represents the difference between sequential frames. This may be used for motion detection, image stabilization, and compression purposes.

Standard CMOS active pixel image sensors for multimedia applications

The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting photons and moving image data across chip. We argue that line widths in standard CMOS have been reduced to the point where it is practical to locate transistors-and hence provide gain-within each detector of an imager fabricated in CMOS. In this paper we describe the image sensors we have been building in this technology. They use far less power, permit random access and can be integrated with arbitrary digital CMOS logic to create low cost single chip video cameras with advanced functionality. Ongoing work includes the development of a color filter array process and the fabrication of a 1024/spl times/1024 pixel sensor for multimedia video and document capture applications.

Software environment for a multiprocessor DSP

In this paper, we describe the software environment for Daytona, a single-chip, bus-based, shared-memory, multiprocessor DSP. The software environment is designed around a layered architecture. Tools at the lower layer are designed to deliver maximum performance and include a compiler, debugger, simulator and profiler. Tools at the higher layer focus on improving the programmability of the system and include a run-time kernel and parallelizing tools. The run-time kernel includes a low-overhead, preemptive, dynamic scheduler with multiprocessor support that guarantees real-time performance to admitted tasks.

Noise performance of a color CMOS photogate image sensor

We report on the noise performance of a color CMOS photogate image sensor that supports two levels of correlated double sampling and has high conversion gain at each pixel. Imager performance is limited by low quantum efficiency and dark current non-uniformity and not by read-out circuit temporal or fixed-pattern noise.

The role of VLSI in multimedia

The opportunity to develop multimedia applications based on compressed video is the result of progress in three areas: standards, networking, and VLSI. Current video coding standards and their underlying algorithms use a variety of techniques to isolate and remove redundancies in the image sequence. Some of these techniques place severe demands on the underlying VLSI technology. Manufacturers of VLSI codecs have chosen a number of different architectural approaches. The advantages and disadvantages of each are discussed in the context of various applications with examples taken from existing or soon to be announced products. The AT&T AVP4000 chip set is described in some detail. Major design challenges included CAD tools for simulation and verification, packaging and the control of power dissipation. >

Event-EMU: an event driven timing simulator for MOS VLSI circuits

An event-driven approach to MOS timing simulation is presented, which has proved to be more efficient and reliable than time-step-based methods. The MOS network is statically partitioned into groups of strongly coupled nodes called regions. Regions are scheduled for evaluation using a priority event queue. Events are predictions of the time at which nodes within a region will change by more than a voltage threshold. Region evaluation is performed using a single modeling step followed by linear relaxation. The simulator has been used to verify the timing and functionality of a number of large (>500 K transistors) VLSI chips. Performance is 2-5 times faster than time-step-based methods and 200-300 times faster than circuit simulation.<<ETX>>

Array configurations for dynamic time warping

In a previous paper an array architecture was revealed for real-time dynamic time warping. An integrated processor was designed and built for use in such an array. This paper discusses reduced arrays which allow a continuum of tradeoffs between speed and circuit complexity. Reduced arrays permit design of fixed-size systems for problems which are unbounded in size.

A high speed array computer for dynamic time warping

Dynamic time warping is an established technique for time alignment and comparison of speech segments in speech recognition. This paper describes a CMOS integrated array processor for computing the dynamic time warp algorithm. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.