Bryant M. Welch

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (\tau_{d} \sim 100ps) GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FETs and switching circuits which indicates that, for equivalent speed-power product operation, GaAs ICs should be about six times faster than Si ICs. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as\tau_{d} = 110ps).

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology

The successful development of a new integrated circuit (IC) technology requires a significant effort in process evaluation. This is particularly true for the high-speed low-power planar GaAs digital IC technology, which involves a relatively new semiconductor material, new processing techniques, and pursues LSI complexity using very-fine-line lithography (1-µm dimensions). This paper contains a review of the strategy employed to monitor and evaluate each of the key process steps, and to evaluate the uniformity of device parameters. The principal process evaluation test structures are discussed along with measurement techniques, and examples of measurement results are given. Our emphasis on measurement automation to facilitate the collection of a large volume of data and their statistical analysis is reflected in the paper. Examples of wafer statistics are given.

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.

The Role of GaAs in High Speed Integrated Circuits

The achievement of ultra high speed VLSI, that is, of integrated circuit chips with complexities of Ng > 104 equivalent logic gates with propagation delays of τd ~ lOOps or less, would make possible computational powers or chip throughput rates hard to imagine by todays standards. The realization of such potential is very difficult, of course, since it necessitates achieving in one circuit and fabrication technology: 1) ultra high speed (very low τd); 2) low power per gate (PD); 3) extremely low dynamics switching energies (power-delay products, PDτd); 4) very high gate densities; and 5) very high process yields (sufficient to allow economic fabrication of such complex parts). 1,2The problem here is the requirement for improvements on both sides of what are classical tradeoffs such as speed-power or lithographic resolution-yield. For example, in silicon MOS the speed may improve by increasing the supply voltage and logic voltage swings in order to increase the average device transconductances or current gain-bandwidth products (fτ’s). Increasing VDD, however, while reducing rd, sharply increases gate power dissipation, PD, and switching energies, PDτd, which would lead to unacceptable power levels in > 104 gate VLSI chips.1,2 Reducing geometry by pressing lithographic resolution is an approach to coping with this speed-power tradeoff, and it improves density as well, but this approach can easily result in unacceptable reduction in yield if pressed too far.

WA-B3 orientation effect on planar GaAs MESFET

Octave-bandwidth power performance from gallium arsenide monolithic amplifiers is reported for the first time. The power output was greater than 300 mW across the band from 4.5 to 9 GHz with greater than 5-dB gain from a monolithic amplifier using a 900-pm periphery GaAs FET. Two-stage 1-W octavebandwidth amplifiers are presently being fabricated and it is anticipated that results of measurements made on these amplifiers will be available for presentation. Our results to date from the two-stage design have shown up to one W over a portion of the 5 to 10-GHz desired band from the 2400-pm periphery output stage. The monolithic integrated circuits were made using selective, direct silicon ion implantation into both chromium-doped and undoped gallium-arsenide substrates grown in-house using liquid encapsulated Czochralski techniques. Both 125 and 300-Kev implants were made through 1000 L% of plasma deposited Si3N4 using AZ1350J photoresist and 2500 L% of phosphorus-silicate glass (PSG) as the beam-stopping materials. This method provides effective isolation between the implanted areas at up to 350 KeV implant energies. The Si3N4 and PSG on Si3N4 are the annealing caps for the implants. An active charge density of about 2.5 X 10l2 cm-2 in the FET channel after gate recessing provides a full channel of current of 450 mA/mm. The fabrication of the FET’s and the circuit elements will be discussed with emphasis on the critical steps of the processing. Results obtained from discrete devices made on both chromiumdoped and undoped substrates will be discussed. The mobility differences in the two materials (4000 and 5000 cm2/V 1 s) affect the small-signal gain of the transistors.