Stephen I. Long

Submicron scaling of HBTs

The variation of heterojunction bipolar transistor (HBT) bandwidth with scaling is reviewed. High bandwidths are obtained by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer or collector-undercut processes or, if contact resistivity is greatly reduced, by reducing the width of the base ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high f/sub max/ and high gains in mm-wave ICs. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency f/sub max/ is 1.1 THz. f/sub max/ will be less than 1 THz if unmodeled electron transport physics produce a >20 dB/decade variation in power gain at frequencies above 110 GHz. Transferred-substrate HBTs have obtained 295 GHz f/sub T/. The substrate transfer process provides microstrip interconnects on a low-/spl epsiv//sub r/ polymer dielectric with a electroplated gold ground plane. Important wiring parasitics, including wiring capacitance, and ground via inductance are substantially reduced. Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz and per-stage gain-bandwidth products over 400 GHz, and master-slave latches operating at 75 GHz.

A 2-GHz subharmonic sampler for signal downconversion

Subharmonic sampling is a discrete-time alternative for the signal downconversion problem. It can be used either to replace a traditional continuous-time mixer in a superheterodyne receiver or can be combined with other discrete-time analog signal processing blocks in novel receiver architectures. We present a 2 GHz bandwidth integrated mixer based on subharmonic sampling. The sampler uses a two-diode topology with a 3 V supply. The downconversion loss for the passive sampler is 1 dB and the total system gain 3 dB. The mixer achieves IIP3 of +16 dBm and -1 dB compression +7 dBm for a single-tone input.

SCALING OF InGaAs/InAlAsHBTs FOR HIGH SPEED MIXED-SIGNAL AND mm-WAVE ICs

High bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer processes, or -if contact resistivity is greatly reduced -by reducing the width of the base Ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high fmax and high gains in mm-wave ICs. Logic gate delays are primarily set by depletion-layer charging times, and neither fτ nor fmax is indicative of logic speed. For high speed logic, epitaxial layers must be thinned, emitter and collector junction widths reduced, current density increased, and emitter parasitic resistance decreased. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency fmax is 1.1 THz. Transferred-substrate HBTs have obtained 295 GHz fτ. Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz, 66 GHz master-slave flip-flops, and 18 GHz clock rate Δ-Σ ADCs.

Experimental analysis of transmission line parameters in high-speed GaAs digital circuit interconnects

Transmission line properties of typical high-speed interconnects were experimentally investigated by fabricating and characterizing coplanar strips on semi-insulating GaAs substrates. The strips have thicknesses of about 2500 AA or 5000 AA and widths of 4, 6, or 8 mu m so as to be representative of on-chip interconnects in high-speed GaAs digital circuits. Measurements are carried out up to 18 GHz, and the pertinent line parameters, such as resistance, capacitance per unit length, and characteristic impedance, are extracted using the measured S-parameters. The measurement results confirm the quasi-TEM properties of such interconnects. In all cases, the measured distributed capacitance and inductance are sensitive to frequency whereas the resistance is found to increase as much as 38% for the widest and thickest conductors. >

Design of Class E power amplifier with nonlinear parasitic output capacitance

The Class E amplifier exploits the output shunt capacitor for charge-storing during the operation cycle. The amplifier works even with a nonlinear output capacitor, but the required component values are different from the values resulting with the linear capacitor. In this paper the equations and component values are solved for the first time for a Class E amplifier having a nonlinear output capacitor with hyperabrupt junction voltage-capacitance characteristics. A hyperabrupt junction capacitor is present especially at the drain-to-bulk junction of practical MOS devices. The results of the analysis are presented in plots providing initial component values for MOS Class E power amplifier design. The procedure is validated with a design example of a single-stage 900 MHz MOS power amplifier operating from a 2-V supply voltage.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (\tau_{d} \sim 100ps) GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FETs and switching circuits which indicates that, for equivalent speed-power product operation, GaAs ICs should be about six times faster than Si ICs. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as\tau_{d} = 110ps).

A high-efficiency class-E GaN HEMT power amplifier at 1.9 GHz

A single stage class-E power amplifier in GaN high electron mobility transistor (HEMT) technology is reported. The circuit operates at 1.9 GHz. At 30-V drain bias, a power-added-efficiency (PAE) of 57% and a maximum output power of over 37dBm was achieved, corresponding to a power density of 5.25W/mm. At 40-V drain bias, an output power of 38.7dBm is achieved at 50% PAE corresponding to a power density of 7.4W/mm

High linearity and high efficiency of class-B power amplifiers in GaN HEMT technology

A 36-dBm high-linearity single-ended common-source class-B monolithic-microwave integrated-circuit power amplifier is reported in GaN high electron-mobility transistor technology. We also describe the design and simulation of highly linear and highly efficient common-source and common-drain class-B power amplifiers. Single-ended class-B amplifiers with bandpass filtering have equivalent efficiency and linearity to push-pull configurations. The common-source class-B circuit demonstrates high linearity, greater than 35 dBc of third-order intermodulation (IM3) suppression and high power-added efficiency (PAE) of 34%. Simulations of common-drain class-B designs predict a PAE of 54% with a superior IM3 suppression of more than 45 dBc over a wider range of bias due to the strong series-series negative feedback offered by the load resistance.

Wave steering in YADDs: a novel non-iterative synthesis and layout technique

In this paper we present a new synthesis and layout approach that avoids the normal iterations between synthesis, technology mapping and layout, and increases routing by abutment. It produces shorter and more predictable delays, and sometimes even layouts with reduced areas. This scheme equalizes delays along different paths, which makes low granularity pipelining a reality, and hence we can clock these circuits at much higher frequencies, compared to what is possible in a conventionally designed circuit. Since any circuit can be clocked at a fixed rate, this method does not require timing-driven synthesis. We propose the logic and layout synthesis schemes and algorithms, discuss the physical layout part of the process, and support our methodology with simulation results.

A 13 W current mode class D high efficiency 1 GHz power amplifier

13 watt Current Mode Class-D (CMCD) with 60% efficiency is presented. This amplifier is the highest power switch mode microwave power amplifier reported to date. The CMCD architecture is an improvement over the Voltage Mode Class-D in that the parasitic reactance in the active device can be absorbed into the tank circuit resulting in a zero voltage switching condition.