Bumho Kim

Design of large scale network simulator using device emulator for Internet of Things

The term “Internet of Things” (IoT) denotes the interconnected of embedded devices designed to leverage data gathered by sensors. These devices are interconnected to transmit information and control instruction via the internet infrastructure. The development of an IoT system is a complex process due to the large scale and widely distribution of deployed wireless node. The simulator provides infrastructure to easily test and debug the algorithms of the IoT applications before they are to be deployed in actual environment. In this paper, we propose the emulation based network simulator architecture which focus on the large scale IoT system. With the proposed simulator architecture, the IoT application developers can reduce cost by cutting the amount of nodes needed for application test and shortens development time required for deploying a large scale IoT system.

A parallel implementation of JPEG2000 encoder on multi-GPU system

There has been an increase in the demand for a high-quality video codec that supports 4K (3,840 × 2,160) or more. JPEG2000 is an important technique for data compression, which has been successfully used in digital cinema and medical application. To process the high workload of JPEG2000 coding for large-scale video data, hybrid CPU/GPU platform is used to obtain high computing power. In this paper, we develop and implementation of the JPEG2000 compression standard in hybrid CPU/GPU platforms. Specifically, we develop multi-GPU implementations of the JPEG2000 encode to obtain high computing power and balance the load between cores and GPUs in the hybrid architecture. In out experiments with multi-GPU, we couple the JPEG2000 codec optimized for multicores and multi-GPUs and achieve high performance of the JPEG2000 compression.

CUDA-based JPEG2000 encoding scheme

JPEG2000 is the international standard for image compression. The rich feature set and the state of the art image compression performance make JPEG2000 an attractive alternative for many applications. Especially JPEG2000 is used in the area for digital cinema and medical image. Although the JPEG2000 provides high compression rates and error tolerance, it is burden for both encoding and decoding. To improve the performance, a parallel computing architecture called CUDA has been receiving a lot of attention recently. In this paper, we attempt to realize a real-time JPEG2000 encoding scheme by using GPUs. We present CUDA algorithms that perform DCDM decomposition, multi-component transform, 2D discrete wavelet transform, and quantization completely on a CUDA device, which brings us significant performance gain on a general CPU without extra cost. In addition, we present CUDA algorithm for performing the color conversion from RGB to XYZ.

GPU-based JPEG2000 decoding scheme for digital cinema

For the digital cinema system specification released by Digital Cinema Initiatives, it was decided to use 2K or 4K images encoded by the JPEG2000 standard. JPEG2000 provides high compression rates and error tolerance, but it is a burden for both encoding and decoding. To improve the decoding performance, a parallel computing architecture called CUDA has been receiving a lot of attention recently. In this paper, we attempt to realize a real-time JPEG2000 decoding scheme for digital cinema using multiple CPU cores and GPUs. We present CUDA algorithms that perform inverse quantization, inverse 2D discrete wavelet transform and inverse irreversible color transform on a CUDA device, which brings us significant performance gain on a general CPU without extra cost.

Implementation of Digital Cinema Mastering System Supporting Multiple Encoding and Wrapping Servers

Digital Cinema Initiatives, LLC (DCI) has established DCI Digital Cinema System Specification (DCSS) which is intended to promote the widespread deployment of digital cinema. We propose a distributed mastering system of digital cinema. It can simultaneously encode Digital Cinema Distribution Master (DCDM) images into JPEG2000 images on remote servers and produce a Digital Cinema Package (DCP) and Key Delivery Message (KDM) that can be satisfied to DCSS. The distributed mastering system covers the packaging process of DCP for digital cinema content and the generating and issuing process of KDM for the DCP.

Implementation of digital cinema mastering system

Digital Cinema Initiatives released a set of technical specifications and requirements for Digital Cinema. We implement the mastering system of digital cinema that produces the Digital Cinema Package (DCP) which has been designed to deliver digital cinema contents such as image, audio and subtitle and Key Delivery Message (KDM) which contains the security information to be used to decrypt the DCP and will be issued to a specific Digital Cinema playback server. We propose a mastering system that covers the packaging process of DCP for Digital Cinema content and the generating and issuing process of KDM to protect the DCP.

Hierarchical Architecture for HEVC Parallel Encoder

The Emerging High Efficiency Video Coding (HEVC) standard offers a significantly better compression rate and higher video quality. HEVC encoders create very high CPU demand, and it is hard for a single core computer to deal with such complex coding computations. To process the high workload of HEVC coding for large-scale video data, the current HEVC draft contains several parallelizing approaches: tile-based parallelization and WPP-level parallelization. In this paper, we adopt additional data parallelism, GOP partitioning, to implement a parallel encoder. We propose the scalable cluster architecture of the HEVC encoder to achieve scalability and a high encoding speed by combining two levels of parallelism, GOP-level parallelism and the HEVC parallel method. The proposed scheme can reduce the large encoding time and significantly improve the coding efficiency. The proposed scalable cluster system is very suitable for high-resolution video such as 4K or 8K containing large amounts of video data.