Burcu Erkmen

Improving classification performance of sonar targets by applying general regression neural network with PCA

The remote detection of undersea mines in shallow waters using active sonar is a crucial subject required to maintain the security of important harbors and cost line areas. The discrimination sonar returns from mines and returns from rocks on the sea floor by human experts is usually difficult and very heavy workload. Neural network classifiers have been widely used in classification of complex sonar signals due to its adaptive and parallel processing ability. In this paper, due to the advantages on fast learning and convergence to the optimal regression surface as the number of samples becomes very large, general regression neural network (GRNN) has been used to solve the problem of classification underwater targets. Principal component analysis (PCA) has been established as a feature extraction method to improve classification performance. Receiver operating characteristic (ROC) analysis has been applied to the neural classifier to evaluate the sensitivity and specificity of diagnostic procedures.

Conic Section Function Neural Network Circuitry for Offline Signature Recognition

In this brief, conic section function neural network (CSFNN) circuitry was designed for offline signature recognition. CSFNN is a unified framework for multilayer perceptron (MLP) and radial basis function (RBF) networks to make simultaneous use of advantages of both. The CSFNN circuitry architecture was developed using a mixed mode circuit implementation. The designed circuit system is problem independent. Hence, the general purpose neural network circuit system could be applied to various pattern recognition problems with different network sizes on condition with the maximum network size of 16-16-8. In this brief, CSFNN circuitry system has been applied to two different signature recognition problems. CSFNN circuitry was trained with chip-in-the-loop learning technique in order to compensate typical analog process variations. CSFNN hardware achieved highly comparable computational performances with CSFNN software for nonlinear signature recognition problems.

A Mixed Mode Neural Network Circuitry for Object Recognition Application

A general purpose Conic Section Function Neural Network (CSFNN) circuitry in Very Large Scale Integration (VLSI) has been designed for an object recognition application. CSFNN is capable of making open and closed decision regions by combining the propagation rules of Radial Basis Functions (RBF) and Multilayer Perceptrons (MLP) on a single neural network with a unique propagation rule. Chip-in-the-loop learning technique was used during the training process. Utilizing mixed-mode hardware techniques, the inputs of the network and the feedforward signals are all analog while the control unit and storage of the network parameters are fully digital. CSFNN circuitry architecture is problem independent and consists of 16 inputs, 16 hidden layer neurons and 8 outputs. Inheriting the merits of CSFNN, the circuitry has good recognition performance on several objects with invariance to pose, lighting, and brightness. The designed hardware achieved a good recognition performance by means of both accuracy and computational time comparable to CSFNN software.

CSFNN optimization of signature recognition problem for a special VLSI NN chip

In this paper, a Conic Section Function Neural Network (CSFNN) based system for signature recognition problem is developed. The purpose of this work is to optimize CSFNN parameters for signature recognition problem to be applied to the VLSI Neural Network (NN) chip. Signature database is constructed after some preprocessing techniques are applied on collected raw data. After the preprocessing phase, the database is introduced to the CSFNN. Then CSFNN parameters are optimized to obtain acceptable signature recognition accuracy for a compact NN chip. Simplicity of the CSFNN structure and the range of parameters make CSFNN suitable for hardware implementation for this problem.

Obtaining decision boundaries of CSFNN neurons using current mode analog circuitry

In this paper, decision boundaries of conic section function neural network (CSFNN) neuron obtained with current mode analog circuitry are presented. The designed circuit computes the radial basis function (RBF) and multilayer perceptron (MLP) propagation rules on a single hardware to form a CSFNN neuron. Decision boundaries, hyper plane (for MLP) and hyper sphere (for RBF), are special cases of CSFNN Networks depending on the data distribution of a given application. Open and closed decision boundaries and intermediate types of these decision boundaries such as hyperbolas and parabolas for CSFNN have been obtained using designed circuitry. Current mode analog hardware has been designed and the simulations of the neuron circuitry have been realized using Cadence with AMIS 0.5 mum CMOS transistor model parameters. Simulation results show that the outputs of the circuits are very accurately matched with ideal curve.

Conic Section Function Neural Networks for Sonar Target Classification and Performance Evaluation Using ROC Analysis

The remote detection of undersea mines in shallow waters using active sonar is a crucial subject required to maintain the security of important harbors and cost line areas. Neural network classifiers have been widely used in classification of complex sonar signals due to its adaptive and parallel processing ability. In this paper, Conic Section Function Neural Networks (CSFNN) is used to solve the problem of classification underwater targets. Simulation results support the ability of CSFNN with computational advantages of traditional neural network structures to utilize highly complex sonar classification problem. Receiver Operating Characteristic (ROC) analysis has been applied to the neural classifier to evaluate the sensitivity and specificity of diagnostic procedures. The ROC curve of the classifier based on different threshold settings demonstrated excellent classification performance of the CSFNN classifier.

Statistical neural network based classifiers for letter recognition

In this paper, Statistical Neural Networks have been proven to be an effective classifier method for large sample and high dimensional letter recognition problem. For this purpose, Probabilistic Neural Network (PNN) and General Regression Neural Networks (GRNN) have been applied to classify the 26 capital letters in the English alphabet. Principal Component Analysis (PCA) has been established as a feature extraction and a data compression method to achieve less computational complexity. The low computational complexity obtained by PCA provides a solution for high dimensional letter recognition problem for online operations. Simulation results illustrate that GRNN and PNN are suitable and effective methods for solving classification problems with higher classification accuracy and better generalization performances than their counterparts.

Process independent automated sizing methodology for current steering DAC

This study introduces a process independent automated sizing methodology based on general regression neural network (GRNN) for current steering complementary metal-oxide semiconductor (CMOS) digital-to-analog converter (DAC) circuit. The aim is to utilise circuit structures designed with previous process technologies and to synthesise circuit structures for novel process technologies in contrast to other modelling researches that consider a particular process technology. The simulations were performed using ON SEMI 1.5 µm, ON SEMI 0.5 µm and TSMC 0.35 µm technology process parameters. Eventually, a high-dimensional database was developed consisting of transistor sizes of DAC designs and corresponded static specification errors obtained from simulation results. The key point is that the GRNN was trained with the data set including the simulation results of ON-SEMI 1.5 µm and 0.5 µm technology parameters and the test data were constituted with only the simulation results of TSMC 0.35 µm technology parameters that had not been applied to GRNN for training beforehand. The proposed methodology provides the channel lengths and widths of all transistors for a newer technology when the designer sets the numeric values of DAC static output specifications as Differential Non-linearity error, Integral Non-linearity error, monotonicity and gain error as the inputs of the network.

FPGA implementation of Differential Evaluation Algorithm for MLP training

In this work, Differential Evolution Algorithm (DEA) is implemented on an embedded systems based on FPGA for the training of multi-layer perceptron (MLP). The classification performance of the MLP trained by DEA on FPGA has been analyzed by using a non-linear database. The MLP performance on FPGA has been compared with that on MATLAB in terms of computational performance and test accuracy. It is proved that DEA is suitable for realizing on FPGA considering simplicity of the algorithm. Simulation results of each component for DEA on FPGA are demonstrated in this paper.

Implementation aspects of Wigner-Hough Transform based detectors for LFMCW signals

Linear Frequency Modulated Continuous Waveform (LFMCW) waveforms are widely used in Low Probability of Intercept (LPI) radars. In this work, Wigner-Hough based transforms are used to detect such waveforms. They are investigated for three aims: Minimizing the effects of Wigner-Ville Distribution (WVD) cross-terms in the transforms, reducing the complexity of hardware implementation and producing the transform results faster. Modified Wigner-Hough Transform (MWHT) is analyzed for the first aim. Sample and hold type intermediate sampling and column-based thresholding techniques are examined for the second and third aims. A signal database (3000 signals with different SNR levels) is created and used to evaluate the performances of 8 alternative methods on probability of detection and probability of chirp rate estimation. The results are compared for -3dB down to -14dB SNR levels. Proposed method is found to be the best candidate to be implemented on Field Programmable Gate Arrays (FPGA) since it produces better performance with less computational density.