Nihan Kahraman

Conic Section Function Neural Network Circuitry for Offline Signature Recognition

In this brief, conic section function neural network (CSFNN) circuitry was designed for offline signature recognition. CSFNN is a unified framework for multilayer perceptron (MLP) and radial basis function (RBF) networks to make simultaneous use of advantages of both. The CSFNN circuitry architecture was developed using a mixed mode circuit implementation. The designed circuit system is problem independent. Hence, the general purpose neural network circuit system could be applied to various pattern recognition problems with different network sizes on condition with the maximum network size of 16-16-8. In this brief, CSFNN circuitry system has been applied to two different signature recognition problems. CSFNN circuitry was trained with chip-in-the-loop learning technique in order to compensate typical analog process variations. CSFNN hardware achieved highly comparable computational performances with CSFNN software for nonlinear signature recognition problems.

Technology independent circuit sizing for standard cell based design using neural networks

This paper presents a neural network (NN) approach for modeling the time characteristics of fundamental gates of digital integrated circuits that include inverter, NAND, NOR, and XOR gates. The modeling approach presented here is technology independent, fast, and accurate, which makes it suitable for circuit simulators. Firstly transient simulations were done in order to obtain delay times for different transistor sizes and different load capacitances using AMIS 1.5 @mm, TSMC 0.25 @mm and TSMC 0.18 @mm technology parameters with HSPICE. These delay time results constitute the inputs of NN while the outputs are transistor sizes. Then, two neural network structures, multilayer perceptron (MLP) and general regression neural network (GRNN), were compared to estimate the transistor sizes. MLP achieved 91 acceptable results through 120 test data where GRNN had 77. The important thing is that the NN is able to generalize the input-output mapping and estimates the outputs for new data which were not applied to the NN for training before. As a conclusion, fundamental gates used for standard cell based VLSI design can be sized for desired delay times using neural networks without knowing SPICE technology parameters.

Technology independent circuit sizing for fundamental analog circuits using artificial neural networks

This study introduces technology independent neural network modeling for fundamental blocks of analog integrated circuits. The circuits modeled here are basic current mirror structures and a differential amplifier which serves as the input stage to most op-amps. Here if a designer defines the output specifications of the circuit, the neural network gives the channel widths (W) of all transistors in the circuit. It must be noted that the neural network in this novel approach is trained with the database including simulations using 1.5 mum, 0.5 mum, 0.35 mum and 0.25 mum technology SPICE parameters and the test data is constituted with simulations using only 0.18 mum technology SPICE parameters which are not applied to the neural network for training beforehand. This shows that neural network is able to give the transistor sizes of circuit for a new unknown technology, independent on the SPICE parameters. As artificial neural network (ANN) structures, General Regression Neural Network (GRNN) and Multilayer Perceptron (MLP) having back propagation algorithm are used. Using new channel widths and lengths obtained from neural networkpsilas output, SPICE simulations of current mirrors and differential amplifier give the desired circuit output specifications for new technology.

A Mixed Mode Neural Network Circuitry for Object Recognition Application

A general purpose Conic Section Function Neural Network (CSFNN) circuitry in Very Large Scale Integration (VLSI) has been designed for an object recognition application. CSFNN is capable of making open and closed decision regions by combining the propagation rules of Radial Basis Functions (RBF) and Multilayer Perceptrons (MLP) on a single neural network with a unique propagation rule. Chip-in-the-loop learning technique was used during the training process. Utilizing mixed-mode hardware techniques, the inputs of the network and the feedforward signals are all analog while the control unit and storage of the network parameters are fully digital. CSFNN circuitry architecture is problem independent and consists of 16 inputs, 16 hidden layer neurons and 8 outputs. Inheriting the merits of CSFNN, the circuitry has good recognition performance on several objects with invariance to pose, lighting, and brightness. The designed hardware achieved a good recognition performance by means of both accuracy and computational time comparable to CSFNN software.

CSFNN optimization of signature recognition problem for a special VLSI NN chip

In this paper, a Conic Section Function Neural Network (CSFNN) based system for signature recognition problem is developed. The purpose of this work is to optimize CSFNN parameters for signature recognition problem to be applied to the VLSI Neural Network (NN) chip. Signature database is constructed after some preprocessing techniques are applied on collected raw data. After the preprocessing phase, the database is introduced to the CSFNN. Then CSFNN parameters are optimized to obtain acceptable signature recognition accuracy for a compact NN chip. Simplicity of the CSFNN structure and the range of parameters make CSFNN suitable for hardware implementation for this problem.

Anti-spoofing in face recognition with liveness detection using pupil tracking

In this work, we focused on liveness detection for facial recognition systems spoofing via fake face movement. We have developed a pupil direction observing system for anti-spoofing in face recognition systems using a basic hardware equipment. Firstly, eye area is being extracted from real time camera by using Haar-Cascade Classifier with specially trained classifier for eye region detection. Feature points have extracted and traced for minimizing persons head movements and getting stable eye region by using Kanade-Lucas-Tomasi (KLT) algorithm. Eye area is being cropped from real time camera frame and rotated for a stable eye area. Pupils are extracted from eye area by using a new improved algorithm subsequently. After a few stable number of frames that has pupils, proposed spoofing algorithm selects a random direction and sends a signal to Arduino to activate that selected directions LED on a square frame that has totally eight LEDs for each direction. After chosen LED has been activated, eye direction is observed whether pupil direction and LEDs position matches. If the compliance requirement is satisfied, algorithm returns data that contains liveness information. Complete algorithm for liveness detection using pupil tracking is tested on volunteers and algorithm achieved high success ratio.

Comparative analog circuit design automation based on multi-objective evolutionary algorithms: An application on CMOS opamp

Automation of analog integrated circuit (IC) design process is very important because of the optimization contradictions. In this study, benefits of multi-objective evolutionary algorithms are presented on two stage operational amplifier design using Harmony Search Algorithm (HSA) and Non-dominated Sorting Genetic Algorithm (NSGA-II). HSA is a new kind of multi-objective evolutionary algorithm which was inspired from the musicians those are looking for the best combination of musical sounds of different instruments that produces most pleasing sound. NSGA-II is an advanced version of genetic algorithm. It combines both current parents and their child population to select new parents. These kinds of design automation tools are required for analog circuit design because there are several contradictions in the design. In this work, transistor sizes which effects all constraints indirectly were automatically synthesized by HSA an NSGA-II.

Process independent automated sizing methodology for current steering DAC

This study introduces a process independent automated sizing methodology based on general regression neural network (GRNN) for current steering complementary metal-oxide semiconductor (CMOS) digital-to-analog converter (DAC) circuit. The aim is to utilise circuit structures designed with previous process technologies and to synthesise circuit structures for novel process technologies in contrast to other modelling researches that consider a particular process technology. The simulations were performed using ON SEMI 1.5 µm, ON SEMI 0.5 µm and TSMC 0.35 µm technology process parameters. Eventually, a high-dimensional database was developed consisting of transistor sizes of DAC designs and corresponded static specification errors obtained from simulation results. The key point is that the GRNN was trained with the data set including the simulation results of ON-SEMI 1.5 µm and 0.5 µm technology parameters and the test data were constituted with only the simulation results of TSMC 0.35 µm technology parameters that had not been applied to GRNN for training beforehand. The proposed methodology provides the channel lengths and widths of all transistors for a newer technology when the designer sets the numeric values of DAC static output specifications as Differential Non-linearity error, Integral Non-linearity error, monotonicity and gain error as the inputs of the network.

Object recognition on general purposed Conic Section Function Neural Network integrated circuit

Automatic recognition using a database obtained from existing objects is getting more importance for industrial and security applications. In this work, the database is collected from the images of various objects that are rotated at different angles have been tested on a general purposed conic section function neural network (CSFNN) integrated circuit. Both hardware results of the integrated circuit and the software results of CSFNN have been compared and applicability of the designed integrated circuit to the object recognition problem has been demonstrated.

Optimum, projected, and regularized extreme learning machine methods with singular value decomposition and L 2 -Tikhonov regularization

The theory and implementation of an extreme learning machine (ELM) have proved that it is a simple, efficient, and accurate machine learning methodology. In an ELM, the hidden nodes are randomly initiated and fixed without iterative tuning. However, the optimal hidden layer neuron number (Lopt) is the key to ELM generalization performance where initializing this number by trial and error is not reasonably satisfied. Optimizing the hidden layer size using the leave-one-out cross validation method is a costly approach. In this paper, a fast and reliable statistical approach called optimum ELM (OELM) was developed to determine the minimum hidden layer size that yields an optimum performance. Another improvement that exploits the advantages of orthogonal projections with singular value decomposition was proposed in order to tackle the problem of randomness and correlated features in the input data. This approach, named projected ELM (PELM), achieves more than 2% advance in average accuracy. The final contribution of this paper was implementing Tikhonov regularization in the form of the L2 -penalty with ELM (TRELM), which regularizes and improves the matrix computations utilizing the L-curve criterion and SVD. The L-curve, unlike iterative methods, can estimate the optimum regularization parameter by illustrating a curve with few points that represents the tradeoff between minimizing the training error and the residual of output weight. The proposed TRELM was tested in 3 different scenarios of data sizes: small, moderate, and big datasets. Due to the simplicity, robustness, and less time consumption of OELM and PELM, it is recommended to use them with small and even moderate amounts of data. TRELM demonstrated that when enhancing the ELM performance it is necessary to enlarge the size of hidden nodes (L) . As a result, in big data, increasing L in TRELM is necessary, which concurrently leads to a better accuracy. Various well-known datasets and state-of-the-art learning approaches were compared with the proposed approaches.