Burkart Voss

A low power sinusoidal clock

This paper describes a low power clock distribution that utilizes sinusoidal clock waveforms and proposes registers that are able to cope with the overlapping clock edges. We can report power savings of 30% to 70% compared with conventional clocking schemes while maintaining traditional static CMOS design styles and logic levels.

State-of-the-art in rapid prototyping for mechatronic systems

This paper will give an overview of state-of-the-art rapid prototyping techniques for mechatronic systems and their enabling technologies. After presenting a taxonomy for the plethora of existing approaches some example prototyping systems and case studies are discussed. With this, the benefits of the emerging new class of system-level prototyping approaches as efficient validation methods for the growing microelectronic part of future mechatronic systems which have to cope with increasing complexity and tighter time-to-market constraints should be pointed out.

Influence of high-level synthesis on average and peak temperatures of CMOS circuits

Abstract The aim of this paper is introducing a new modified high-level synthesis (HLS) technique resulting in reduction of the power dissipation in CMOS circuits leading to lowering the peak and the average temperature of the designed chip. The presented approach enables us designing contemporary electronic systems with reduction of the peak and average power consumption, so the reliability of the system can be improved. In the present method, the initial HLS is performed by the ASAP algorithm [The Synthesis Approach to Digital System Design, 1992]. In the next stage, acceptable increase of the toggling time of chosen functional units (without exceeding the system throughput — the latency is constant) leads to the possibility of decreasing their supply voltages. These chosen functional units are determined by the inserting idle operations with interchanging (IIOI) algorithm. This approach leads to decreasing the power dissipated in the chosen functional units and finally their peak and average temperature is lowered.

Impeller integrated measurement of cavitation erosive aggressiveness

For the online measurement of erosive cavitation aggressiveness in hydraulic turbomachinery a system is developed, which is based on the measurement of the structure born noise. The direct coupling of the piezoelectric sensor on the exposed impeller provides a minimisation of the disturbance of the signal. A signal processing device and a transmission system have to be integrated into the rotating system too. This system may be used to detect critical cavitating operation conditions or for active control.

State-of-the-Art in Rapid Prototyping for Mechatronic Systems

Abstract This paper will give an overview of state-of-the-art rapid prototyping techniques for mechatronic systems and their enabling technologies. After presenting a taxonomy for the plethora of existing approaches some example prototyping systems and case studies are discussed. With this, the benefits of the emerging new class of system-level prototyping approaches as efficient validation methods for the growing microelectronic part of future mechatronic systems which have to cope with increasing complexity and tighter time-to-market constraints should be pointed out.

Impeller Integrated Measurement of Cavitation Erosive Aggressiveness

Abstract For the online measurement of erosive cavitation aggressiveness in hydraulic turbomachinery a system is developed, which is based on the measurement of the structure born noise. The direct coupling of the piezoelectric sensor on the exposed impeller provides a minimisation of the disturbance of the signal. A signal processing device and a transmission system have to be integrated into the rotating system too. This system may be used to detect critical cavitating operation conditions or for active control.

Solving problems of low dimensional devices at the system level

We describe an approach to an electronic system based on assumptions made regarding low dimensional devices. Systems using those devices will have three major obstacles: The variation of the parameters is increasing, the reliability of the individual switching elements decreases and the interconnection between those elements will prove to be more difficult than ever. To overcome those obstacles we consider an approach using locally interconnected very simple elements in a neuromorphic way. Because analog implementations of weighting and addition can be made very simple, we examine a theoretical analog implementation of linear threshold gates as the simple elements needed for a neuromorphic approach. We derive the dependence of the tolerance against statistical variations on the interconnect density and show, that one can increase the tolerance against parameter variations with an increase of the interconnect density. Finally we conclude the discussion with an example of a Full Adder based on monostable bistable transition logic elements (MOBILE) build with resonant tunneling diodes (RTD). We show that it is possible to trade off the number of interconnections and computing elements against the robustness against statistical variations.