Clemens Schlachta

On timing and power consumption in inductively coupled on-chip interconnects

This work analyses the effects on timing and power consumption of the inductive coupling in long high-frequency on-chip interconnects. By means of extensive simulations it is shown that the common assumptions used until now when considering only line inductance effects do not hold. In fact, signal integrity, voltage glitches and cross-talk, signal delay, rise and fall times, as well as power dissipation strongly depend on the mutual inductances and the input data toggling pattern.

Reconfiguration requirements for high speed wireless communication systems

This paper focuses on the reconfiguration requirements of hardware platforms for high speed wireless communication systems. Due to the underlying trade-off between flexibility and efficiency, many reconfigurable hardware solutions and FPGA implementations are prone to significant energy and performance penalties in comparison to application specific hardware designs. These penalties can only be alleviated by designing reconfigurable architectures for selected applications fields, since each application field has only a limited set of flexibility requirements. In this paper the analysis is conducted for emerging wireless communication standards based on the OFDM (Orthogonal Frequency Division Multiplexing) or CDMA (Code Division Multiple Access) transmission technique. The requirements for the physical and the medium access layers are analyzed separately. Focus is also set on different market segments.

Impeller integrated measurement of cavitation erosive aggressiveness

For the online measurement of erosive cavitation aggressiveness in hydraulic turbomachinery a system is developed, which is based on the measurement of the structure born noise. The direct coupling of the piezoelectric sensor on the exposed impeller provides a minimisation of the disturbance of the signal. A signal processing device and a transmission system have to be integrated into the rotating system too. This system may be used to detect critical cavitating operation conditions or for active control.

A CMOS compatible charge recovery logic family for low supply voltages

In this work we will introduce an enhanced, CMOS-compatible adiabatic logic family based on a new diode element for charge recovery. This diode element uses bipolar transistors to reduce the diode forward voltage losses in existing charge recovery logic families allwoing the use at lower supply voltages. Based on this element the CMOS compatible, static adiabatic logic familiy biQSERL is introduced.

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

This paper presents the realisation of a hardware-in-the-loop system to investigate the performance of different cellular automata (CA) structures. The system is applied to regular lattice CAs and to small-world CAs, which are expected to expose better characteristics than lattice automata due to their nature-inspired structure. CA functionality is evolved using a genetic algorithm (GA) implemented as a distributed Java program running on a host computer. The performance evaluation of whole generations of individual automata is transferred to a specialised hardware architecture on an FPGA-board in order to speed up this process. For this, a customisable version of an automaton is residing on the board and personalisation data can be downloaded to it. The objective of the approach is to gather qualitative and quantitative data on the differences between the two types of CAs. We discuss two CA implementations, one of a lattice CA and one of a small-world CA. Their properties are characterised and their integration into the overall evaluation system is described.

Accurate capture of timing parameters in inductively-coupled on-chip interconnects

With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose severe difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.