Byoung Gun Choi

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.

A Dual-band CMOS RF Front-end for 2.4/5.2 GHz Applications

A dual-band RF front-end operating at 2.4 and 5.2 GHz is proposed. The dual-band RF front-end consists of a low noise amplifier and a single balance mixer which can be switched to operate at 2.4 and 5.2 GHz with the same hardware. In order to get the good performances at both frequency bands, the LNA uses a switched effective inductance in the input matching. The proposed RF front-end is designed with the 0.18 mum CMOS process with a supply voltage of 1.8 V while dissipating a power of 16 mW. The front-end has conversion gains of 28 dB and 32 dB, DSB noise figure of 3.9 dB and 3.1 dB at 10 MHz with RF frequency of the 2.4 GHz and 5.2 GHz, respectively

Low-voltage, Low-power and High-gain Mixer Based on Unbalanced Mixer Cell

A low-voltage, low-power and high-gain mixer core structure based on the unbalanced mixer cell or square-law mixer cell for 5GHz wireless LAN applications is presented in this paper. To reduce power dissipation, a new single-balanced mixer was proposed which operates under a low supply voltage and with the current reuse technique. The circuit was designed with a 0.18mum CMOS process. The designed down-conversion mixer has a maximum conversion gain of 22dB with LO power of -2.5dBm. However, with small LO power of -10dBm, -15dBm and -20dBm the mixer shows a moderate conversion gain of 14.9dB, 10dB and 5.1dB, and an input P1dB of -14dBm, -9.5dBm and -4.5dBm, and an input IP3 of -4.5dBm, 0dBm and 5dBm, respectively. The designed mixer including a bias circuit consumes 1.2mA under a 1.5V supply voltage. The chip size including pads is 0.77mm times 0.81mm

Dual-band LNA for 2.4/5.2GHz applications

A dual-band low noise amplifier (LNA) which can operate at both 2.4GHz and 5.2GHz frequency band is proposed. Input matching, noise matching and narrow gain are achieved at 2.4GHz and 5.2GHz frequency band by switching the equivalent inductance and resistance of input and output circuits. The proposed LNA is designed in a TSMC 0.18um CMOS technology with a supply voltage of 1.5V. The LNA has gain of 11.8 dB and 16 dB, noise figure of 3.6 dB and 2.5 dB at 2.4GHz and 5.2GHz frequency band respectively while dissipating power of 4.5 mW at both frequency bands.

A 5.8 GHz SiGe HBT direct-conversion I/Q-channel sub-harmonic mixer for low power and simplified receiver architecture

This paper presents a novel SiGe HBT sub- harmonic direct-conversion mixers for C-band wireless LAN application. The proposed down conversion mixer consists of single level I/Q-channel mixers and 90° phase shifters for each RF and LO input. Since the proposed sub-harmonic mixer requires only single ended RF and LO signal sources for generating I/Q base-band signals, the RF front-end can be greatly simplified compared to the fully differential RF front-end architecture from LNA and VCO to mixer. The measured conversion gain and input P1dB are 13.6 dB and -15 dBm, respectively at 5.8 GHz RF signal and 2.9 GHz LO signal. I/Q mismatches caused by LO and RF 90° phase shifters and I/Q- channel mixers are less than 5° and 0.5 dB in phase and amplitude mismatches. Each I/Q-channel sub-harmonic mixer consumes 6.2 mA from a 2.7 V supply.

A direct-conversion receiver for low-voltage low-power multi-band UWB with a novel single-level mixer

A CMOS direct-conversion receiver including a low noise amplifier and a novel single transistor stacked mixer is proposed in this paper. The LNA has a small signal gain of 12-10 dB and a noise figure of 4.2-4.8 dB in 3-7 GHz range. The conversion gain and the input P1dB of the mixer are 3-6.5 dB and -10 dBm, respectively with the multiband RF signals. The LNA consumes 9.2 mA and the mixer consumes 4.3 mA under 1.8 V supply voltage, respectively

Device and circuit optimization of PHEMT MMIC LNA for low power consumption

This paper presents a low power PHEMT monolithic LNA for C-band applications. A two-stage PHEMT MMIC low noise amplifier with power consumption of 18 mW, low noise figure as low as 1.7 dB with gain 18 dB at 5.8 GHz, has been designed using S- and noise parameters and large signal model. The input return loss and output return loss are better than -17 dB and -20 dB at 5.8 GHz, while drawing only 6 mA from a 3 V supply. This PHEMT MMIC LNA has superior DC power performance while still maintaining low noise figure, compared with other HEMT LNAs at the frequency range.

A novel CMOS down-conversion mixer with current reuse technique

A novel low voltage and power mixer topology for 5GHz wireless LAN applications is presented in this paper. To reduce power dissipation, a novel mixer topology with a low supply voltage and using the current reuse technique is designed using a 0.18 /spl mu/m CMOS process. The designed down-conversion mixer has a conversion gain of 7.5dB, a P1dB of -16Bm and an IIP3 of -6dBm, respectively, with LO power of -7dBm while consuming 1.6mA under a 1.5V supply voltage. The chip size including pads is 0.77mm /spl times/ 0.81mm.

Study of the electroless deposition of Ni for betavoltaic battery using PN junction without seed layer

The method and conditions of Ni plating were optimized to maximize the output of a betavoltaic battery using radioactive 63Ni. The difference of the short circuit currents between the pre- and post deposition of 63Ni on the PN junction was 90 nA at the I-V characteristics. It is suspected that the beta rays emitted from 63Ni did not deeply penetrate into the PN junction due to a Ni seed layer with a thickness of 500 A. To increase the penetration of the beta rays, electroless Ni plating was carried out on the PN junction without a seed layer. To establish the electroless coating conditions for 63Ni, nonradioactive Ni was deposited onto a Si wafer without flaws on the surface. This process can be applied for electroless Ni plating on a PN junction semiconductor using radioactive 63Ni in further studies.

A low voltage SiGe HBT up-conversion mixer for 5.8 GHz WLAN

A new low voltage doubly balanced mixer topology for 5.8 GHz wireless local area network applications is presented in this paper. To reduce the supply voltage, a single stacked transistor mixer topology is designed with 50 GHz f/sub T/ SiGe HBT process. The designed up-conversion mixer has a conversion gain of 4.2 dB, an OP1 dB of -6 dBm and LO to RF isolation greater than 31 dB while consuming DC power of 13.2 mW under a 1.2 V low supply voltage. The chip size including pads is 0.96 mm /spl times/ 0.92 mm.