Sung Weon Kang

A new fabrication method of silicon field emitter array with local oxidation of polysilicon and chemical-mechanical-polishing

In this paper, we describe the fabrication of single crystal silicon field emitter arrays. Emission tips have been fabricated by a novel method which uses chemical-mechanical-polishing (CMP) and local polysilicon oxidation for gate electrodes and gate dielectrics, respectively. By this method, we can shrink the radius of gate aperture without increasing gate leakage current, and get a clean cut edge of gate electrode. The anode emission current measured from the 1024 tips array was about 17 /spl mu/A (16 nA/tip) at a gate voltage of 64 V.

Focusing and leveling system using position-sensitive detectors for the wafer steppers

An optical focus and leveling system for ETRI KrF excimer laser stepper is developed using position sensitive detectors (PSD) and optical magnification method. This type of detection method showed focusing and leveling accuracies of about +/- 0.1 micrometers and +/- 1.0 arcsec (+/- 0.5 X 10-5 rad) respectively. Also, we confirmed experimentally the autofocus system has +/- 0.15 micrometers signal stability within the controlled temperature range of +/- 0.1 degree(s)C. In this paper, we report the design concepts of the focusing and leveling system and the characteristics of the system parameter applied to ETRI KrF excimer laser stepper.

Fabrication and characterization of silicon field emitter arrays by spin-on-glass etch-back process

Silicon field emitter arrays have been fabricated by a novel method employing a two-step tip etch and spin-on-glass etch-back process using double layered thermal/tetraethylorthosilicate oxides as a gate dielectric. Partial etching was performed by low viscosity photoresist coating and O2 plasma ashing in order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The height and the radius of the fabricated emitter was about 1.1 μm and less than 100 A, respectively. The anode emission current from a 256 tip array was 23 μA (i.e., 90 nA/tip) at a gate voltage of 60 V. The turn-on gate voltage was 40 V. The gate current was less than 0.1% of the total current (i.e., gate current and anode current).

Emission characteristics of silicon field emitter arrays fabricated by spin-on-glass etch-back process

The fabrication process and emission characteristics of silicon field emitter arrays (FEAs) for flat panel display are described. FEAs have been fabricated by a novel method which consists of two-step tip etch and spin-on-glass (SOG) etch-back processes using double layered thermal/tetraethylorthosilicate (TEOS) oxides as a gate dielectric. A small gate aperture with low gate leakage current could be fabricated with the process. The anode emission current measured from the 1024 tips array was about 300 /spl mu/A (292 nA/tip) at a gate voltage of 70 V and the turn-on voltage was 49 V.

Novel structure of a silicon field emission cathode with a sputtered TiW gate electrode

A novel technique for a gated silicon field emission cathode is proposed in order to decrease the spacing between the tip and the gate electrode of the device, which leads to low voltage operation. This technique is based on the filling characteristics of the sputtered Ti0.1W0.9 layer, which is used as the gate electrode in the shadowed area surrounding the tip with good step coverage. This process is completely compatible to conventional 1.2 μm complementary metal–oxide–semiconductor standard processes. The experimental results indicate that the diameter of the gate hole is greatly reduced to a subhalf-micron dimension (∼0.4 μm) even when starting with an initial mask size of 1.2 μm. The I–V characteristics of the cathodes show low turn-on voltages (∼25 V) in high vacuum (<3.0×10−7 Torr). The Fowler–Nordheim plots also show good linearity.

Polycrystalline Silicon Field Emitter Arrays With A Gated Structure

Gated polycrystalline silicon field emitter arrays have been fabricated by using a combined dry and wet etching technique for tip formation and a photoresist etchback process for gate opening. The fabricated emitter with a tip radius of -100 A showed electron emissions at a gate voltage of 45 V, comparable to single crystalline silicon tips processed with a sharpening oxidation. The developed method can be applicable to glass-based field emitter displays with semiconductor IC technologies.

A novel structure of silicon field emission cathode with sputtered TiW for gate electrode and TEOS oxide for gate dielectric

A novel structure of silicon field emission cathode with the narrow spacing between tip and gate electrode is proposed, leading to a low voltage operation. It utilizes the filling characteristics of the sputtered Ti/sub 0.1/W/sub 0.9/ beneath the disc-shaped tip-mask oxide with good step-coverage. TEOS (tetraethylorthosilicate) oxide is used for gate dielectric and it shows good leakage characteristics. Without advanced lithography technology, the gate hole diameter is greatly reduced to sub-half micron of /spl sim/0.4 /spl mu/m from the initial tip-mask size of /spl sim/1.2 /spl mu/m. Uniform and stable silicon field emission cathode is obtained using well-established VLSI process technologies. I-V characteristics of the cathodes show low turn-on voltages of /spl sim/30 V.

A novel structure of silicon field emission cathode with sputtered TiW for gate electrode

A novel techniques for a gated silicon field emission cathode is proposed in order to decrease the spacing between tip and gate electrode of the device, leading to low voltage operation. This technique is based on the penetration of the sputtered Ti/sub 0.1/W/sub 0.9/ for the gate electrode into the shadowed area surrounding the tip with good step coverage, and is completely compatible to the conventional 1.2 /spl mu/m CMOS standard processes. The experimental results indicate that the gate hole diameter is greatly reduced to sub-half micron (/spl sim/0.4 /spl mu/m) from the initial mask size (/spl sim/1.2 /spl mu/m), and I-V characteristics of the cathodes show low turn-on voltages (/spl sim/25 V) in ultrahigh vacuum (<3.0/spl times/10/sup -7/ Torr) and the good linearity of Fowler-Nordheim plots.