Byoung-Soo Choi

Pregnenolone sulfate enhances spontaneous glutamate release by inducing presynaptic Ca2+-induced Ca2+ release

Pregnenolone sulfate (PS) acts as an excitatory neuromodulator and has a variety of neuropharmacological actions, such as memory enhancement and convulsant effects. In the present study, we investigated the effect of PS on glutamatergic spontaneous excitatory postsynaptic currents (sEPSCs) in acutely isolated dentate gyrus (DG) hilar neurons by use of a conventional whole-cell patch-clamp technique. PS significantly increased sEPSC frequency in a concentration-dependent manner without affecting the current amplitude, suggesting that PS acts presynaptically to increase the probability of spontaneous glutamate release. However, known molecular targets of PS, such as α7 nicotinic ACh, NMDA, σ1 receptors and voltage-dependent Ca(2+) channels, were not responsible for the PS-induced increase in sEPSC frequency. In contrast, the PS-induced increase in sEPSC frequency was completely occluded in a Ca(2+)-free external solution, and was significantly reduced by either the depletion of presynaptic Ca(2+) stores or the blockade of ryanodine receptors, suggesting that PS elicits Ca(2+)-induced Ca(2+) release (CICR) within glutamatergic nerve terminals. In addition, the PS-induced increase in sEPSC frequency was completely occluded by transient receptor potential (TRP) channel blockers. These data suggest that PS increases spontaneous glutamate release onto acutely isolated hilar neurons via presynaptic CICR, which was triggered by the influx of Ca(2+) through presynaptic TRP channels. The PS-induced modulation of excitatory transmission onto hilar neurons could have a broad impact on the excitability of hilar neurons and affect the pathophysiological functions mediated by the hippocampus.

A Linear-Logarithmic CMOS Image Sensor With Adjustable Dynamic Range

A new pixel structure is proposed for wide dynamic range CMOS image sensors. A pixel based on a three-transistor active pixel sensor has two linear responses and a logarithmic response using additional circuits. The photogate surrounding the n+/p-sub photodiode exists for the second linear response. The logarithmic response is due to the biased MOS cascode. The proposed pixel was designed and fabricated using a 0.35-μm 2-poly 4-metal standard CMOS process. The dynamic range of the pixel is higher than 106 dB. A test chip with a pixel pitch of 10 × 10 μm2 and a 160 × 120 pixel array is evaluated.

Current calibration algorithm for bolometer-type uncooled infrared image sensor using pipeline signal processing

In this paper, we propose a pixel averaging current calibration algorithm for reducing fixed pattern noise due to the deviation of bolometer resistance. To reduce fixed pattern noise (FPN), averaging current calibration algorithm by which output current of each bolometer reference pixel is averaged by the averaging current calibration is suggested. The principle of algorithm is that average dark current of reference pixel array is subtracted by a dark current of each active pixel array. After that, the current difference with information of pixel deviation is converted to voltage signal through signal processing. To control the current difference of pixel deviation, a proper calibration current is required. Through this calibration algorithm, nano-ampere order dark currents with small deviations can be obtained. Sensor signal processing is based on a pipeline technique which results in parallel processing leading to very high operation. The proposed calibration algorithm has been implemented by a chip which is consisted of a bolometer active pixel array, a bolometer reference pixel array, average current generators, line memories, buffer memories, current-to-voltage converters (IVCs), a digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Proposed bolometerresistor pixel array and readout circuit has been simulated and fabricated by 0.35μm standard CMOS process.

Wide dynamic range and high-sensitivity CMOS active pixel sensor using output voltage feedback structure

This paper presents a novel high-sensitivity and wide dynamic range complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) with an overlapping control gate. The proposed APS has a high-sensitivity gate/bodytied (GBT) photodetector with an overlapping control gate that makes it possible to control the sensitivity of the proposed APS. The floating gate of the GBT photodetector is connected to the n-well and the overlapping control gate is placed on top of the floating gate for varying the sensitivity of the proposed APS. Dynamic range of the proposed APS is significantly increased due to the output voltage feedback structure. Maximum sensitivity of the proposed APS is 50 V/lux•s in the low illumination range and dynamic range is greater than 110 dB. The proposed sensor has been fabricated by using 2-poly 4-metal 0.35 μm standard CMOS process and its characteristics have been evaluated.

Effects of aperture size on the performance of CMOS image sensor with pixel aperture for depth extraction

Effects of aperture size on the performance of CMOS image sensor with pixel aperture for depth extraction are investigated. In general, the aperture size is related to the depth resolution and the sensitivity of the CMOS image sensor. As the aperture size decreases, the depth resolution is improved and the sensitivity decreases. To optimize the aperture size, optical simulation using the finite-difference time-domain method was implemented. The optical simulation was performed with various aperture sizes from 0.3 μm to 1.1 μm and the optical power with the incidence angle as a function of the aperture size was evaluated. Based on the optical simulation results, the CMOS image sensor was designed and fabricated using 0.11 μm CMOS image sensor process. The effects of aperture size are investigated by comparison of the simulation and the measurement results.

Optimization of linear-logarithmic CMOS image sensor using a photogate and a cascode MOSFET for reducing pixel response variation

Recently, CMOS image sensors (CISs) have become more and more complex because they require high-performances such as wide dynamic range, low-noise, high-speed operation, high-resolution and so on. First of all, wide dynamic range (WDR) is the first requirement for high-performance CIS. Several techniques have been proposed to improve the dynamic range. Although logarithmic pixel can achieve wide dynamic range, it leads to a poor signal-to-noise ratio due to small output swings. Furthermore, the fixed pattern noise of logarithmic pixel is significantly greater compared with other CISs. In this paper, we propose an optimized linear-logarithmic pixel. Compared to a conventional 3-transistor active pixel sensor structure, the proposed linear-logarithmic pixel is using a photogate and a cascode MOSFET in addition. The photogate which is surrounding a photodiode carries out change of sensitivity in the linear response and thus increases the dynamic range. The logarithmic response is caused by a cascode MOSFET. Although the dynamic range of the pixel has been improved, output curves of each pixel were not uniform. In general, as the number of devices increases in the pixel, pixel response variation is more pronounced. Hence, we optimized the linear-logarithmic pixel structure to minimize the pixel response variation. We applied a hard reset method and an optimized cascode MOSFET to the proposed pixel for reducing pixel response variation. Unlike the conventional reset operation, a hard reset using a p-type MOSFET fixes the voltage of each pixel to the same voltage. This reduces non-uniformity of the response in the linear response. The optimized cascode MOSFET achieves less variation in the logarithmic response. We have verified that the optimized pixel shows more uniform response than the conventional pixel, by both simulation and experiment.

Extraction of depth information for 3D imaging using pixel aperture technique

A 3dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. In this paper, extraction of depth information for 3D imaging using pixel aperture technique is presented. An active pixel sensor (APS) with in-pixel aperture has been developed for this purpose. In the conventional camera systems using a complementary metal-oxide-semiconductor (CMOS) image sensor, an aperture is located behind the camera lens. However, in our proposed camera system, the aperture implemented by metal layer of CMOS process is located on the White (W) pixel which means a pixel without any color filter on top of the pixel. 4 types of pixels including Red (R), Green (G), Blue (B), and White (W) pixels were used for pixel aperture technique. The RGB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RGB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Size of the pixel for 4-tr APS is 2.8 μm × 2.8 μm and the pixel structure was designed and simulated based on 0.11 μm CMOS image sensor (CIS) process. Optical performances of the pixel aperture technique were evaluated using optical simulation with finite-difference time-domain (FDTD) method and electrical performances were evaluated using TCAD.

CMOS image sensor for extracting depth information using offset pixel aperture technique

The 3-dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. Many techniques have been reported for 3D imaging using various methods such as time of fight (TOF), stereo vision, and structured light. These methods have limitations such as use of light source, multi-camera, or complex camera system. In this paper, we propose the offset pixel aperture (OPA) technique which is implemented on a single chip so that the depth can be obtained without increasing hardware cost and adding extra light sources. 3 types of pixels including red (R), blue (B), and white (W) pixels were used for OPA technique. The aperture is located on the W pixel, which does not have a color filter. Depth performance can be increased with a higher sensitivity because we use white (W) pixels for OPA with red (R) and blue (B) pixels for imaging. The RB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Previously, we proposed the pixel aperture (PA) technique based on the depth from defocus (DFD). The OPA technique is expected to enable a higher depth resolution and range compared to the PA technique. The pixels with a right OPA and a left OPA are used to generate stereo image with a single chip. The pixel structure was designed and simulated. Optical performances of various offset pixel aperture structures were evaluated using optical simulation with finite-difference time-domain (FDTD) method.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.