Byunghoo Jung

Pulse generator design for UWB IR communication systems

This paper presents a low power impulse generator design for ultra-wideband (UWB) impulse radio (IR) applications. Simple digital delay elements and a NAND gate are used to generate short duration pulses. A varactor controls the pulse width of the generated signal. The low-end of the spectrum of the generated pulse is attenuated using an integrated high-pass filter while the high-end of the spectrum is extended using a peaking inductor. This makes efficient use of the FCC spectral mask. The designed pulse generator in 0.18 /spl mu/m TSMC CMOS technology consumes 0.4 mW at 100 MHz pulse repetition rate, and the spectral efficiency is more than 55%. The proposed IR generator topology gives a spectral efficiency improvement of more than 14% relative to the topology without the peaking inductor.

A new noncoherent UWB impulse radio receiver

This letter analyzes the implementation issues related to coherent receivers for UWB impulse radio with a special emphasis on timing and jitter problems. We propose a new jitter tolerant receiver design that is easy to implement. Analytical BER analysis and simulations verify that the performance of the proposed receiver is comparable to that of a correlator-based receiver that includes jitter. The new design is a promising candidate for low-cost low-power UWB IR receiver implementations.

/spl Sigma/High-frequency LC VCO design using capacitive degeneration

In this paper, we evaluate the high-frequency performance limitations of traditional LC voltage-controlled oscillators (VCOs) that use a cross-coupled negative resistance cell and propose a new topology that overcomes these limitations. The proposed cell is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties combined with its small effective capacitance enable low-power low-noise high-frequency VCO implementations. The proposed topology is demonstrated through a 20-GHz fully integrated LC VCO implemented in the IBM SiGe 0.25-/spl mu/m BiCMOS process. A comparison of its figure of merit with previously reported 20-GHz VCOs shows the effectiveness of the proposed topology.

Novel CMOS low-loss transmission line structure

As operating speeds increase low-loss interconnect structures such as transmission lines become critical in the design of RF and high speed digital circuits. This paper presents a novel low-loss transmission line structure. We discuss the importance of transmission line structures, including coplanar and grounded coplanar structures. Grounded coplanar waveguide (GCPW) structures are enhanced to reduce the substrate loss. The primary goal of new interconnect topology, stacked GCPW (S-GCPW), is to reduce the loss by shaping the electric fields under the signal line. 3D electromagnetic wave simulations are used to verify the efficacy of the new transmission line structures. The insertion loss for a 4 mm long S-GCPW structure is 1.62 dB@50 GHz (0.41dB/mm) while the insertion loss for a 4 mm long traditional GCPW structure is 3.28 dB (0.82 dB/mm) in a 0.12 /spl mu/m SOI CMOS technology.

A wide tuning range VCO using capacitive source degeneration

This paper presents a wide tuning range LC voltage controlled oscillator with a new differential negative resistance cell that uses capacitive source degeneration. Traditional differential negative resistance cells use two transistors where the drains are cross-connected to the corresponding gates and the sources are ac grounded. This structure has a fairly large parasitic shunt capacitance. This effective parasitic capacitance combined with the fixed portion of the varactor and the inductor parasitic capacitance limits the tuning range and the maximum size of allowable inductor that is crucial for the large output swing. This paper shows that if the sources of the differential negative resistance cell are capacitively degenerated such that the effective parasitic capacitance is much smaller than that of traditional structures, then the tuning range can be increased or alternately the output swing can be increased for a given tuning range. An appropriate degenerating capacitance and device geometry can be selected to optimize the performance. The tradeoff between negative resistance and effective parasitic capacitance has also been considered. To verify this concept, a 5.3 GHz VCO with 21.5% tuning range and -106 dBc/Hz phase noise at 1 MHz offset from 5 GHz has been designed using the TSMC 0.25 /spl mu/m CMOS process.

A 20GHz VCO with 5GHz tuning range in 0.25 /spl mu/m SiGe BiCMOS

This paper presents a 20 GHz VCO with 5 GHz tuning range in 0.25 /spl mu/m SiGe BiCMOS. A differential capacitive emitter degenerated structure is used as a negative resistance cell that has extremely low parasitic capacitance. The VCO core consumes 9 mW, and the measured phase noise at 1 MHz offset is -101.2 dBc/Hz.

Power optimized LC VCO and mixer co-design

A capacitively source degenerated buffer provides a negative impedance and can be used as the negative resistance cell in the voltage-controlled oscillator (VCO). This eliminates the need for a negative resistance cell within the VCO itself. Eliminating the negative resistance cell within the VCO allows us to reduce the overall power consumption for a design that combines a VCO with a follow-on mixer stage. Further, as the VCO directly drives the mixer, the input capacitance of the mixer can be incorporated into the degeneration capacitor of the negative resistance cell. In other words, the mixer and VCO when co-designed can result in a significantly more optimal design. This paper presents the design for a prototype 4 GHz LC VCO and a mixer that has been designed for a 5 GHz RF and 1 GHz IF radio application in the 0.18 /spl mu/m TSMC CMOS technology.

Designing LC VCOs using capacitive degeneration techniques

In this paper, we present a detailed analysis of VCOs using a capacitively degenerated negative resistance cell. The negative resistance cell using capacitive degeneration has a higher maximum attainable oscillation frequency and a smaller equivalent shunt capacitance when compared to the widely used cross-coupled negative-gm cell. These properties are of particular interest for the design of high-frequency and/or wide tuning range VCOs. The negative resistance provided by a traditional capacitively degenerated negative resistance cell is lower than that provided by a cross-coupled negative-gm cell. We present an active capacitive degeneration topology that overcomes this limitation. To validate this circuit topology we use two test vehicles. The first test vehicle is a 5.3 GHz VCO designed in a 0.25 μm CMOS technology and the second test vehicle is a 20 GHz VCO designed in a 0.25 μm BiCMOS technology. Measurement and simulation results from both test vehicles effectively demonstrate the efficacy of the capacitive degeneration technique.

A novel noise optimization design technique for radio frequency low noise amplifiers

In this paper we present a novel noise optimization design technique using voltage boosting for low-noise amplifiers (LNAs). High performance FET LNAs use inductive source degeneration to generate the real part of the input impedance without using a noisy resistor. Normally the source inductance is adjusted to meet the 50 /spl Omega/ power matching condition. In this paper we show that if the source degenerating inductance value is adjusted such that the impedance is larger than the source resistance, the output noise power can be reduced. The maximum input resistance is limited by the quality factor of the gate inductor and transconductance saturation at high gate bias voltage due to short channel effects. An appropriate input resistance and device geometry can be selected to optimize the NF. The tradeoff between noise figure and linearity has also been considered. To verify our design concepts a prototype MESFET LNA with 1.65-dB noise figure and 5.2-dBm third order input intercept point has been designed and tested. It consumes 12mW from a 2.0-V power supply.