Ramesh Harjani

OASYS: a framework for analog circuit synthesis

A hierarchically structured framework for analog circuit synthesis is described. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation and from actual fabricated analog ICs based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits. >

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converters efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9 % for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.

A low-power CMOS VGA for 50 Mb/s disk drive read channels

We describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50 Mb/s. The VGA provides a 25 db gain variation along an ideal exponential gain to control voltage curve and 30 dB of gain control if ideal exponential characteristics is not absolutely necessary. The VGA achieves the necessary exponential gain to control voltage characteristics intrinsically using only MOS transistors as a single unit to reduce power and area consumption. Overall power consumption is less than 10 mW for the VGA circuit excluding the off-chip buffer circuits. >

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.

Partial positive feedback for gain enhancement of low-power CMOS OTAs

Four circuit schemes that use partial positive feedback for gain enhancement in CMOS OTAs are examined. These circuit schemes are classified as type I and type II circuits. Type I circuits use a differential input pair with positive feedback and type II circuits use a active load with positive feedback. As the primary emphasis of these circuits is for micropower operation, the circuits have been examined in detail in the subthreshold region. A comparison of the primary characteristics of these circuits together with simulation results are presented. It is shown that partial positive feedback is a viable technique to increase the gain and the bandwidth of CMOS OTAs. Without any increase in power, a 20 dB increase in gain and a 5X improvement in bandwidth is feasible.

CMOS switched-op-amp-based sample-and-hold circuit

This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feed through error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-opamps are designed and fabricated in a 2-/spl mu/ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated ICs and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits.

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range

This paper presents a technique to efficiently supply power over a wide power range using a fully-integrated on-chip converter for dynamic voltage scaling (DVS) based applications. All components, including filter elements, are integrated on-chip. To achieve high efficiency the converter adaptively switches between different modes of operation by detecting the output current. The design, implemented in IBM 130 nm CMOS technology, achieves a peak efficiency of 77% at reduced temperature of 8°C and has a maximum efficiency of 74.5% under normal operating conditions. The converter supplies power over a 450X output power range (0.6 mW to 266 mW). To the best of our knowledge, this is the largest reported power range for a high-efficiency, fully-integrated on-chip power converter to date.

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-/spl mu/m CMOS process are given. The circuit uses a quiescent supply current of 0.2 /spl mu/A and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies.

Analog/RF physical layer issues for UWB systems

Ultra-wideband communications systems offer unique challenges and opportunities for RF circuit design. Proper understanding of the trade-offs that system specifications impose upon the circuit designer is essential in optimizing a system for UWB. The defining attribute of UWB is the wide fractional bandwidth of the signal. This wide bandwidth can be achieved in several ways: with carrierless systems, with a wide-bandwidth single carrier spread-spectrum system, with a multi-carrier system such as OFDM, via frequency hopping, or via some combination of these methods. This paper provides detailed impact analysis of wide fractional bandwidth on RF frontend circuits and examines the various tradeoffs. In particular, wide-bandwidth channels limit the instantaneous Q allowable in the signal path. This requires modifications of the traditional narrowband design methods. Some of the issues discussed in this paper include: issues of broadbanding, power impact, fast hopping tradeoffs, power amplifier, and antenna issues.

Feasibility and performance region modeling of analog and digital circuits

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.