Byungkyu Song

Efficacy of intraoperative dexmedetomidine infusion on emergence agitation and quality of recovery after nasal surgery

BACKGROUND Emergence agitation is common after nasal surgery. We investigated the effects of intraoperative dexmedetomidine infusion on emergence agitation and quality of recovery after nasal surgery in adult patients. METHODS One hundred patients undergoing nasal surgery were randomized into two groups. The dexmedetomidine group (Group D, n=50) received dexmedetomidine infusion at a rate of 0.4 μg kg(-1) h(-1) from induction of anaesthesia until extubation, while the control group (Group C, n=50) received volume-matched normal saline infusion as placebo. Propofol (1.5-2 mg kg(-1)) and fentanyl (1 μg kg(-1)) were used for induction of anaesthesia, and desflurane was used for maintenance of anaesthesia. The incidence of agitation, haemodynamic parameters, and recovery characteristics were evaluated during emergence. A 40-item quality-of-recovery questionnaire (QoR-40) was provided to patients 24 h after surgery. RESULTS The incidence of agitation was lower in Group D than Group C (28 vs 52%, P=0.014). Mean arterial pressure and heart rate were more stable in Group D than in Group C during emergence (P<0.05). Time to extubation, bispectral index, and respiratory rate at extubation were similar between the groups. Global QoR-40 score at 24 h after surgery was higher in Group D (median [range], 183 [146 -198]) compared with Group C (178 [133-196]) (P=0.041). CONCLUSIONS Intraoperative infusion of dexmedetomidine provided smooth and haemodynamically stable emergence. It also improved quality of recovery after nasal surgery.

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 × faster sensing speed, 1.12 × lower read energy, and 1.13 × smaller area when compared with the best value of design parameters of other sense amplifiers.

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vref is selected after fabrication, and the calibrated switch control bit, which contains Vref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

Sensing circuit optimization using different type of transistors for deep submicron STT-RAM

In this paper, we propose an optimal combination of transistor types in the conventional sensing circuit. A sensing margin, which determines the read yield of STT-RAM, is sensitive to the Vth type of several transistors in the sensing circuit. Thus, the optimization of the sensing circuit using different types of transistors is important for designing the sensing circuit in STT-RAM. Using industry compatible 45-nm model parameters, Monte Carlo HSPICE simulation results show that the conventional sensing circuit optimized using different types of transistors achieves read access pass yield enhancement of 10% when compared to the conventional sensing circuit using typical transistors.

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory

A global reference-circuit (RC), which means one RC is shared with many sensing circuits (SC), is being considered for high-bandwidth STT-RAMs because of the low power consumption and small area characteristic. However, using the global RC for high-bandwidth STT-RAMs causes a droop effect and coupling noise effect, leading to the significant performance degradation. Thus, the validity of using the global RC should be identified. In this paper, the local RC and various global RCs are introduced, and compared in aspects of area, sensing time, and power consumption. By classification of the merits and demerits of various RCs, we present the following requirements of proper RC for high-bandwidth STT-RAMs: 1) small area, 2) no performance degradation, 3) low power consumption, and 4) process variation tolerant reference signal generation.

Equalization scheme analysis for high-density spin transfer torque random access memory

As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.

Comparative analysis of using planar MOSFET and FinFET as access transistor of STT-RAM Cell in 22-nm technology node

As technology node scaling, FinFET becomes the substitution for planar MOSFET due to several merits of FinFET such as superior gate controllability, large on-current, and low variability. For the reasons, using FinFET as access transistor of spin-transfer-torque random access memory (STT-RAM) cell should be analyzed. This paper compares using planar MOSFET and FinFET as access transistor of STT-RAM cell and concludes which device is more proper solution for high write and read yields.