Hyun-Kook Park

Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Phase-change random access memory (PRAM) is considered to be one of the most promising storage class memory candidates. In this paper, several circuit techniques are introduced to satisfy the target yield and sensing time requirements of an 8-Gb PRAM. First, we propose a temperature-tracking reference current generator to compensate for the variation in data current caused by the change in the resistance of phase-change materials. Second, an adaptive precharge scheme to solve the problem of large parasitic resistances and capacitances of a global bitline is proposed. Finally, we introduce noise compensation schemes to reduce coupling noise. The verification of the proposed circuit techniques is performed by HSPICE simulation using the 0.25- μm model parameters used in peripheral circuit of Samsungs 20 nm PRAM technology. The sensing scheme using temperature tracking reference current generator achieves 9.32σ ( ~ 100%) of read access pass yield in 8-Gb PRAM and 99 ns of the sensing time is achieved using the adaptive precharge scheme and noise compensation schemes.

Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM

Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25-

Memory devices, memory systems, and related operating methods

\mu \text{m}

Resistive memory device and method programming same

model parameters used in the peripheral circuit of Samsung’s 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.