C.F.M. Loureiro

A 1 GSPS VME data acquisition module

In the following a new data acquisition architecture is proposed allowing high sampling rates along with a large memory data buffer. The modular design allows up to four 250 MHZ, 8-bit acquisition channels to operate in an interleaved way, achieving 1 GSPS. Each channel can acquire continuously up to 3 MBytes of data (or 12 MBytes when interleaved). Since several modules can coesist in an acquisition system, provision was made for several parallel operations, including trigger distribution and download of digital signal processing programs. The module will be used in a dedicated acquisition system for the reflectometry diagnostic on the Asdex-Upgrade tokamak.

On-site developed components for control and data acquisition on next generation fusion devices

Publisher Summary This chapter discusses the main requirements, principles and technical issues to be taken into account in the conceptual design of the control and data acquisition systems of new fusion experiments. The control and data acquisition system of a new generation fusion device should be conceived in a distributed, integrated, hierarchical, manufacturing independent, and user-friendly approach, taking advantage of the most recent improvements in networking, front-end processing, and database management. Data acquisition is performed by several dedicated subsystems designed in a function oriented structure and linked by fast networks. This architecture allows to develop the subsystems independently, to minimize the data traffic in the network, and to increase the system safety. It also provides upgrading capacity to meet new experimental requirements during the life of the experiment and flexibility to include new technologies.

An Easy Procedure for Calibrating Data Acquisition Systems Using Interleaving

Interleaving data acquisition channels is a well-known and interesting technique to achieve higher acquisition rates. However, to obtain the expected benefits, a careful look at the interleaving technique and to mismatches that can lead to unwanted harmonic distortion and noise is essential. In this paper we discuss the methods used to interleave existing high-speed, 250 MSPS 8-bit acquisition channels, and the results obtained. The methods presented allowed a good relative channel calibration in amplitude (amplitude mismatch under 0.1 lsb) and in time (time mismatch between acquisition channels in the ps range, under the specified maximum jitter for the ADC used). A dynamic, by software, amplitude level signal-dependent adjustment procedure is also suggested for signals with rich frequency content that can substantially improve the quality of the acquired signal when using interleaved channels. The techniques presented provide good results even in the presence of noise.

Innovative modular high-speed data-acquisition architecture

This paper reports on the development of a new high-speed modular data-acquisition architecture, capable of covering the most demanding applications concerning sampling time and the combination of sampling time with memory-per-channel capability, along with sophisticated functionality for easy system integration. The proposed modular architecture also directly addresses the common problem of trigger generation and delivery by implementing a large (several tens of megabytes), low-cost circular memory. This allows for a large delay in the delivery time of the trigger signal (up to tens of milliseconds while acquiring data at 1 GSPS) without incurring any data lost or dead time.

A high-speed transputer-based data acquisition system

A 250 MHz 8-bit transputer-based data acquisition VME bus module is described. This module has been designed as the acquisition node of a transputer-based real-time processing and data reduction system for the reflectometry diagnostic in the ASDEX Upgrade tokamak experiment. The architecture of the board is detailed, emphasizing the advantages of using recently delivered devices, like fast synchronous FIFOs, in a mixed ECL/TTL data acquisition architecture. It is shown that the implemented architecture leads naturally to the implementation of hardware triggers that allow the acquisition channels to operate as stand-alone modules in a self-triggered, self-timed, data acquisition mode. The advantages of using transputers as local control and processing units are discussed. The use of the board in the reflectometry diagnostic and the general processing goals of the system are presented together with data characterizing the performance of the acquisition channels.

Testing high-resolution digitizers using conventional signal sources

This paper presents a method to evaluate the performance of high-resolution digitizers using signal sources that may be of lower specification than the device under test. The method is based on the best fitting of a straight line to a set of measures of the signal to noise ratio, excluding the harmonic distortion, obtained for several amplitudes of the test signal. Theoretical derivations and both computer simulated and experimental data are included. It is shown that the effective number of bits estimated using this method is not affected by the leakage effects that occur when other frequency domain tests are used and the input signal is sampled along a non-integer number of cycles.

On-line trigger processing for a small animal RPC-Pet camera

A complex task for pet cameras is the design of an appropriate coincidence-detection trigger system as it usually encompasses coincidences in a large number of channels and tight time specifications. Those requirements are even greater for a resistive plate chamber (RPC)-based detector technology as the time window specification is quite small (in the order of a few hundred picoseconds) and the number of coincidence-channels can be quite large.

Multiprocessor data acquisition system

A VME-based multiprocessor system primarily designed as the data acquisition system for a position-sensitive, driftless, gas proportional scintillation counter for X-ray astronomy is described. The counter is built around a nine-photocathode photomultiplier tube. The system was specified so that an external signal triggers the acquisition of nine analog data channels at a 20-MHz rate, with all channels operating in parallel and synchronized. For each data frame a preprocessing algorithm runs in each processor and is followed by a validation routine in the tenth processor. According to the validation decision data may be discarded or collected by the host VME computer. For this purpose a special parallel architecture was developed in which a digital signal processor is dedicated to each data channel, taking care of the acquisition, the preprocessing, and the validation algorithms. Physically the system consists of a set of VME boards each containing two TMS320C26 DSPs and two 20-MHz data acquisition channels. >

Evaluation of corneal nerves morphology for diabetic peripheral neuropathy assessment

The evaluation of corneal nerve morphology by optical methods may form the basis of a simple, non-invasive technique for early diagnosis and accurate assessment of peripheral diabetic neuropathy. Currently, corneal nerves can be imaged in vivo using corneal confocal microscopy, an expensive technique that is only available at large medical units. Our goal is to develop an optical technique for peripheral neuropathy assessment, through corneal nerves imaging, based on simple, easy to operate and widespread instrumentation. This technique will be built upon automatic algorithms for corneal nerves segmentation and morphometric analysis and an optical confocal module for recording corneal nerves images using a standard slit-lamp, the most commonly used instrument in ophthalmic practice to observe the anterior eye. Here we present the current status and results of this ongoing project.

Innovative high-speed data acquisition architecture

This paper reports on the development of a new high speed modular data acquisition architecture, capable of covering the most demanding applications in what concerns sampling time and the combination of sampling time with memory per channel capability, along with sophisticated functionality for easy system integration. The modular architecture proposed also addresses directly the common problem of trigger generation and delivery by implementing a large (several tens of Mbytes), low cost, circular memory. This allows for a large delay in the delivery time of the trigger signal (up to tens of milliseconds while acquiring data at 1 GSPS) without incurring any data lost or dead time.