C. Grace

Continuously live image processor for drift chamber track segment triggering

The first portion of the BABAR experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of <0.7 mm and a per-segment event time resolution of <70 ns. The TSF system consists of 24 hardware-identical TSF modules. These are the most complex modules in the BABAR trigger. On each module, fully parallel segment finding proceeds in 20 pipeline steps. Each module consists of a 9U algorithm board and a 6U interface board. The 9U printed circuit board has 10 layers and contains 0.9 million gates implemented in 25 FPGAs, which were synthesized from a total of 50,000 lines of VHDL. The boards were designed from the top-down with state-of-the-art CAD tools, which included gate-level board simulation. This methodology enabled production of a flawless board with no intermediate prototypes. It was fully tested with basic test patterns and 10/sup 5/ simulated physics events.

Design and implementation of the level 1 charged particle trigger for the BABAR detector

The environment of the high-luminosity PEP-II machine poses unique design challenges for the trigger system of the BABAR detector. These led to the adoption of a real-time parallel pipelined architecture for the trigger electronics which departs significantly from previous implementations at conventional e/sup +/e/sup -/ experiments. One challenge for the trigger designer lies in detecting low multiplicity physics events with high efficiency while keeping the background rate within the data acquisition limits. To achieve this difficult task, creative and innovative high-speed trigger algorithms were designed, simulated and implemented in Field Programmable Gate Arrays on printed circuit boards, using advanced CAD/CAE tools. The simulation results indicate that these algorithms will be able to perform all required tasks quickly and efficiently. This paper describes the design of the Level 1 Drift Chamber Trigger System of the BABAR detector, including the trigger algorithms, design and test methodology of the implementation, as well as test and simulation results.

A real-time transverse momentum discriminator for the BABAR level 1 trigger system

The transverse momentum discriminator module (PTDM) is one of the three main modules used in the level 1 charged particle trigger system of the BABAR detector at PEP-II. It provides trigger decisions for charged particles with a transverse momentum, P/sub t/, greater than a configurable threshold. The transverse momentum discrimination algorithm works by evaluating the curvature of the charged tracks in the 1.5 T axial magnetic field. The capabilities of the PTDM are key to a stable and efficient operation of the BABAR experiment even under severe background conditions.

A fast low noise CMOS charge sensitive preamplifier for column parallel CCD readout

A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for a 100ns readout cycle time is achieved for a power consumption of 5mW. Novel design techniques used in this circuit will be presented in detail along with measurement results obtained on the prototype.

Multiplexed oversampling digitizer in 65 nm CMOS for column-parallel CCD readout

A digitizer designed to read out column-parallel charge-coupled devices used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined analog-to-digital converter and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The analog-to-digital converter multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the imager. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The analog-to-digital converter exhibits 188 μV-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65-nm CMOS process. The digitizer will be applied to the development of a proof-of-principle 2D, 10 Gigapixel/s X-ray detector.

Development of a fast framing detector for electron microscopy

A high frame rate detector system is being developed to enable fast real-time data analysis of scanning diffraction experiments in scanning transmission electron microscopy (STEM). This is an end-to-end development that encompasses the data producing detector, data transportation, and real-time processing of data. The detector will consist of a central pixel sensor that is surrounded by annular silicon diodes. Both components of the detector system will synchronously capture data at almost 100 kHz frame rate, which produces an approximately 400 Gb/s data stream. Low-level preprocessing will be implemented in firmware before the data is streamed from the National Center for Electron Microscopy (NCEM) to the National Energy Research Scientific Computing Center (NERSC). Live data processing, before it lands on disk, will happen on the Cori supercomputer and aims to present scientists with prompt experimental feedback. This online analysis will provide rough information of the sample that can be utilized for sample alignment, sample monitoring and verification that the experiment is set up correctly. Only a compressed version of the relevant data is then selected for more in-depth processing.

Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

Development of next-generation nuclear physics integrated readout electronics for GRETINA

Advances in nuclear structure studies using gamma-ray spectroscopy are being driven by large-volume, electrically-segmented germanium detectors such as the Gamma Ray Energy Tracking In-Beam Nuclear Array (GRETINA) and, in the future, GRETA. GRETINA employs 28 close-packed high-purity germanium detectors with 36 segments each assembled on a support structure covering 1-π of the target position. GRETA will use the same type of detectors as GRETINA and it will cover the full 4-π. To fully realize the potential of these detectors in terms of energy and position resolution, event rate and usability, a next-generation integrated readout electronics system is required with an emphasis on channel density, data throughput, low noise, low power and testability. Addressing these areas of research will have a positive impact in these large spectrometer arrays. The present research includes (a) the design and characterization of charge sensitive amplifier application specific integrated circuit (ASIC) for smaller dimension, lower noise and power dissipation, (b) design of a detector-mounted, low-power small form factor signal digitization to address issues in the analog-to-digital (ADC) linearity and to reduce the cable plant, including the design and characterization of a high speed ADC ASIC and (c) strategies to filter the microphonic noise using adaptive filtering. In this paper we will report the status of this research. Also, observe that although the target of this research is GRETINA, these approaches could be used in other Nuclear Science experiments.

Radiation-Tolerant Code-Density Calibration of Nyquist-Rate Analog-to-Digital Converters

A radiation-tolerant analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookup table. The algorithm uses techniques to increase tolerance to soft errors both during convergence and during normal operation. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to an 80-MS/s, 10-bit prototype Pipelined ADC implemented in 65-nm CMOS technology. The ADC is implemented with two additional stages to provide calibration data. The calibration algorithm improves measured integral nonlinearity from -4.11/1.32 least significant bits (LSB) to -0.29/0.30 LSB at a 10-bit level.

Code-density calibration of Nyquist-rate analog-to-digital converters

An analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookup table. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to a 12-stage prototype Pipelined ADC implemented in 65 nm CMOS technology and is able to improve measured integral nonlinearity from -5.31/1.02 least significant bit (LSB) to -0.24/0.31 LSB at a 10-bit level, an improvement of over three effective bits.