H. von der Lippe

The SVX4 integrated circuit

Abstract A first prototype of the SVX4 readout IC with enclosed transistor layout for radiation tolerance has been fabricated in a commercial 0.25 μm bulk CMOS process. The SVX4 is intended to instrument the CDF and D0 Run IIB silicon strip detector upgrades at Fermilab. The design and test results are discussed.

A High-Speed Multi-Channel Readout for SSPM Arrays

Solid-state photomultiplier (SSPM) arrays are a new technology that shows great promise to be used in PET detector modules. To reduce the number of channels in a PET scanner, it is attractive to use resistor dividers, which multiplex the number of channels in each module down to four analog output channels. It is also attractive to have SSPMs with large pixels (3×3 or 4×4 mm2). However, large area SSPMs have correspondingly large capacitances (up to 1 nF) and directly coupling them to a resistive network will create a low-pass filter with a high RC time constant. In order to overcome this, we have developed an application specific integrated circuit (ASIC) that “hides” the intrinsic capacitance of the SSPM array from a resistive network with current buffers, significantly improving the rise time of the SSPM signals when connected to the resistive network. The ASIC is designed for a wide range of SSPM sizes, up to 1 nF (equivalent to 4×4 mm2), and for input currents of 1 to 20 mA per channel. To accommodate various sizes of SSPM pixels, the ASIC uses adjustable current sources (to keep the feedback loop stable). A test ASIC has been fabricated that has 16 input channels, an internal resistor divider array that produces four analog outputs, 16 buffers that isolate the SSPM capacitance from the resistor array, and four output buffers that can drive 100 ohm loads. Thus, detector modules based on SSPMs and this ASIC should be compatible with the block detector readout electronics found in many PET cameras. Tests of this ASIC show that its rise time is <; 2 ns (and it will thus not significantly degrade the ~7 ns rise time of the SSPM pixels) and that the analog decoding circuitry functions properly.

SNAP focal plane

The proposed SuperNova/Acceleration Probe (SNAP) mission will have a two-meter class telescope delivering diffraction-limited images to an instrumented 0.7 square-degree field sensitive in the visible and near-infrared wavelength regime. We describe the requirements for the instrument suite and the evolution of the focal plane design to the present concept in which all the instrumentation -- visible and near-infrared imagers, spectrograph, and star guiders -- share one common focal plane.The proposed SuperNova/Acceleration Probe (SNAP) mission will have a two-meter class telescope delivering diffraction-limited images to an instrumented 0.7 square-degree field sensitive in the visible and near-infrared wavelength regime. We describe the requirements for the instrument suite and the evolution of the focal plane design to the present concept in which all the instrumentation -- visible and near-infrared imagers, spectrograph, and star guiders -- share one common focal plane.

Continuously live image processor for drift chamber track segment triggering

The first portion of the BABAR experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of <0.7 mm and a per-segment event time resolution of <70 ns. The TSF system consists of 24 hardware-identical TSF modules. These are the most complex modules in the BABAR trigger. On each module, fully parallel segment finding proceeds in 20 pipeline steps. Each module consists of a 9U algorithm board and a 6U interface board. The 9U printed circuit board has 10 layers and contains 0.9 million gates implemented in 25 FPGAs, which were synthesized from a total of 50,000 lines of VHDL. The boards were designed from the top-down with state-of-the-art CAD tools, which included gate-level board simulation. This methodology enabled production of a flawless board with no intermediate prototypes. It was fully tested with basic test patterns and 10/sup 5/ simulated physics events.

Electronics for the BaBar central drift chamber

The central drift chamber for the BaBar detector at the SLAC B-factory is based on a hexagonal cell design with 7104 cells arranged in 40 layers and drift gas helium:isobutane (80%:20%). Performance optimization and integration requirements led to an electronics design that mounts the amplifier-discriminator and digitizing circuitry directly on the endplate. High channel density is achieved using a 4-channel custom amplifier-discriminator IC and an 8-channel custom CMOS TDC/FADC IC on a single circuit board. Data read from the front ends are multiplexed on 4 fiber optic links, and prompt trigger data are sent out continuously on 24 links. Analysis of cosmic ray data demonstrates that the electronics design meets the performance goals for the BaBar drift chamber. The final electronics were installed on the drift chamber in July, 1998. Installation of BaBar on beamline is scheduled for March, 1999.

A low power, wide dynamic range multigain signal processor for the SNAP CCD

A four-channel custom chip designed for reading out the CCDs of the SNAP satellite visible imager is presented. Each channel consists of a single-ended to differential converter followed by a correlated double sampler and a novel multi slope integrator. The output signal is differentially brought out of the chip by an output buffer. This circuit is designed to operate at room temperature for test purpose and at 140K, which will be the operating temperature. The readout speed is 100kHz. The 16-bit dynamic range is covered using 3 gains each with a 12 bit signal to noise ratio. The prototype chip, implemented in a 0.25 /spl mu/m CMOS technology, has a measured readout noise of 7/spl mu/V rms at 100kHz readout speed, a measured non-linearity of /spl plusmn/0.025% and a power consumption of 6.5mW.

Wide-Field Surveys from the SNAP Mission

The Supernova / Acceleration Probe (SNAP) is a proposed space-borne observatory that will survey the sky with a wide-field optical/near-infrared (NIR) imager. The images produced by SNAP will have an unprecedented combination of depth, solid-angle, angular resolution, and temporal sampling. For 16 months each, two 7.5 square-degree fields will be observed every four days to a magnitude depth of AB=27.7 in each of the SNAP filters, spanning 3500-17000Å. Co-adding images over all epochs will give AB=30.3 per filter. In addition, a 300 square-degree field will be surveyed to AB=28 per filter, with no repeated temporal sampling. Although the survey strategy is tailored for supernova and weak gravitational lensing observations, the resulting data will support a broad range of auxiliary science programs.

Design and implementation of the level 1 charged particle trigger for the BABAR detector

The environment of the high-luminosity PEP-II machine poses unique design challenges for the trigger system of the BABAR detector. These led to the adoption of a real-time parallel pipelined architecture for the trigger electronics which departs significantly from previous implementations at conventional e/sup +/e/sup -/ experiments. One challenge for the trigger designer lies in detecting low multiplicity physics events with high efficiency while keeping the background rate within the data acquisition limits. To achieve this difficult task, creative and innovative high-speed trigger algorithms were designed, simulated and implemented in Field Programmable Gate Arrays on printed circuit boards, using advanced CAD/CAE tools. The simulation results indicate that these algorithms will be able to perform all required tasks quickly and efficiently. This paper describes the design of the Level 1 Drift Chamber Trigger System of the BABAR detector, including the trigger algorithms, design and test methodology of the implementation, as well as test and simulation results.

A real-time transverse momentum discriminator for the BABAR level 1 trigger system

The transverse momentum discriminator module (PTDM) is one of the three main modules used in the level 1 charged particle trigger system of the BABAR detector at PEP-II. It provides trigger decisions for charged particles with a transverse momentum, P/sub t/, greater than a configurable threshold. The transverse momentum discrimination algorithm works by evaluating the curvature of the charged tracks in the 1.5 T axial magnetic field. The capabilities of the PTDM are key to a stable and efficient operation of the BABAR experiment even under severe background conditions.

A CCD clock controller ASIC using novel design techniques integrated in a CMOS 0.8μm SOI high voltage process

An ASIC designed to provide the clock signals to the focal plane CCDs for the SNAP satellite project is presented. A prototype has been implemented in a CMOS 0.8 mum SOI high voltage process in order to accommodate a 20 V output swing. The circuit consists of a main charge pump multiplying the 4 V power supply voltage +/-16 V followed by a controlled current source setting the clock voltage plateaus. A bridge of switches provides the clock voltage transitions at the output. This circuit is designed to operate at room temperature for test purpose and at 140 K, which will be the operating temperature. Novel design techniques used in this chip will be presented in detail along with measurement results obtained on the prototypes.