C. K. Ramesha

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82i?area saving, 1.57i?speedup and 3.63i?less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.

Solution to the Tic-Tac-Toe Problem Using Hamming Distance Approach in a Neural Network

Paper focuses on developing an algorithm using a Hamming Distance Classifier in Neural Networks to find the most optimal move to be made in the Tic-Tac-Toe problem such that the game always ends in a win or a draw. The basic step involves an eight-class Hamming network which has nine inputs corresponding to each cell of the grid and eight outputs respectively. The algorithm computes the Hamming Distance of the current input configuration as compared to the weight matrix and the maximum of the output corresponds to the minimum distance. The iterative step is carried out to anticipate the next move for every possible current move. The hamming distance of all the iterations is added to basic step and the gross maximum gives the most profitable move. The algorithm proceeds such that the neural network prefers to itself win rather than preventing the opponent from winning in least possible moves.

Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture

Memristor based nanocrossbar layer fabricated on CMOS layer has shown tremendous potential as high density memory and in reconfigurable logic architectures. Instead of having predesigned Configurable Logic Blocks (CLBs) and memory for reconfiguration as in FPGA, they can be instantiated in nanocrossbar memory as the need arises. We have shown in this paper, the novel design of NOR block as basic unit of computation for in-memory calculations to implement on CMOL FPGA architecture. This block implements its function using material implication. The proposed scheme is against the naturally arising boolean logic based NOR block in CMOL FPGA.

Hybrid CMOS-memristor based FPGA architecture

It is understood that FPGAs suffer in terms of area, performance and power consumption relative to ASICs. With increasing demand for greater density and lower power consumption in memory devices, memristors have emerged as a cutting-edge alternative to transistor based circuitry. The basic issue of static power consumption in routing architecture is solved here as there is no static current flow in memristors; they hold their state when no power is applied. In this paper, a single memory cell based on hybrid technology is designed using TEAM model in memristors. In addition, the design of a configurable logic block (CLB), which can be used to fabricate a hybrid CMOS - Memristor FPGA architecture is explained. The paper also presents an Interconnect design based on hybrid technology which is very easy to design and flexible to program. As the routing architecture is the most important factor determining system speed, this hybrid interconnect could create a new generation of fast and power efficient memristor based FPGAs.

Performance evaluation of energy based spectrum sensing in multipath fading channel for cognitive radio system

Cognitive radio will drive the future of wireless/radio communication by efficient utilization of underutilized spectrum (vacant space). Spectrum sensing and primary user detection is the main challenge in cognitive radio systems. Energy based sensing is a common spectrum sensing method for cognitive radio since the information about the licensed user signal are not required for the detection process. In this paper, the performances of the energy detection technique are analyzed over Gaussian Noise Channel and different fading channels such as Rayleigh and Rician Channel based on Receiver Operating Characteristics (ROC) and probability of detection (Pd) versus Signal to Noise Ratio (SNR) curves through simulation using MATLAB. The analysis is validated with theoretical results.

Performance analysis of superior selective reporting-based energy efficient cooperative spectrum sensing in cognitive radio networks

Abstract We study the energy efficiency of superior selective reporting-based schemes for spectrum sensing in cognitive radio networks. We first consider the superior selective reporting (SSR) scheme proposed earlier in the literature, and derive the achievable throughput, energy consumption and energy efficiency (EE) of the SSR scheme. We propose the maximization of EE for the SSR scheme as a multiple variable-based, non-convex optimization problem and provide approximations to reduce it to a quasi-convex optimization. We highlight that the errors due to these approximations are negligible. The SSR scheme is designed to optimize the energy consumption, which enhances the EE. Alternatively, EE can be improved by increasing the achievable throughput. Towards this end, we propose a novel variation on the SSR scheme called the opportunistic SSR (OSSR) scheme, and carry out its EE analysis. We study the tradeoff between performances of the SSR and OSSR schemes – the implicit tradeoff between achievable throughput and energy consumption, and discuss the regimes where OSSR is preferred over SSR and vice-versa, in terms of the EE. Also, through an extensive numerical study, we show that both schemes outperform the conventional schemes that employ the OR and AND fusion rules, in terms of energy efficiency.

Realistic directional antenna suite for cooja simulator

The use of directional antennas in wireless ad-hoc and sensor networks is gaining immense popularity due to its features such as increased coverage range, security, enhanced throughput and energy efficiency. Only a few simulators such as Network Simulator 2 (NS2), NS3 and Qualnet are currently providing directional antenna support. Recently, a directional antenna model has been implemented in Cooja simulator, which we have enhanced further to provide a realistic approach for simulations relying on directional communications. In this paper, we propose a directional antenna suite which also has the features to support smart antennas. The proposed suite allows to load simulation results of desired antenna radiation pattern, simulated using High Frequency Structure Simulator (HFSS) or any other antenna design simulators. The simulations carried out in the proposed suite, to analyze the performance of directional antennas in terms of coverage range, packet delivery ratio and Received Signal Strength Indicator (RSSI) is in utmost accuracy with the real-time measurements. Using this newly designed suite eases the code portability from simulation to real-time deployment.

Adder implementation in reconfigurable resistive switching crossbar

Memristors are being investigated by researchers as a replacement for the present non-volatile memory architectures and logical operation units. Such a shift to memristor based devices will allow for the development of computer architectures which are highly advanced than the classical von Neumann architecture. In this paper, we have proposed an N-input stateful-NOR operation on Complementary Resistive Switch (CRS) based crossbar array. The logic is implemented on nanocrossbar arrays where connection and control is provided by underlying CMOS layer. A study of reconfigurable logic using stateful-NOR gate on CRS based crosssbar array and an implementation of 1-bit adder has been presented which has then been extended for N-bit adder. A comparison of 8-bit adder implementation with existing adder architectures on crossbar shows reduction in the number of execution steps required and number of CRS cells used for implementation.

Reconfigurable beam scanning using hexagonal slotted parasitic patch antenna array

In this paper, we propose a pattern reconfigurable microstrip antenna with improved beam scanning range. The antenna is a Yagi-Uda structure with center square shaped driven patch and two hexagonal slotted tunable parasitic patches placed on each side of the driven element. The radiation properties of parasitic patches are changed by varying the capacitance of varactor diodes loaded in hexagonal slot. The proposed antenna works in three possible modes namely, reflector-director, director-reflector and broadside at 2.45 GHz. The simulation result shows that the main beam of antenna radiation can be continuously scanned from 18° to 42° and -18° to -42° in reflector-director and director-reflector mode respectively. For broadside mode, the main beam of antenna is steered to 0°, with a gain of 3.55 dBi. The beam scanning range has been further enhanced, by applying truncated ground plane, achieving a symmetrical beam scanning from -46° to 46°.

A reconfigurable microstrip cross parasitic patch antenna with two-dimensional beam scanning capability

A reconfigurable planar cross parasitic patch antenna is designed and simulated to achieve continuous two-dimensional beam scanning at 2.45 GHz. The antenna realizes complete azimuthal beam scanning with a maximum elevation angle of 34°. This antenna consists of a central driven element and four hexagonal slotted tunable parasitic patches placed on each side of the driven element. The effective electrical size of the parasitic element is changed with respect to the driven element, by varying the capacitance of varactor diodes loaded in the hexagonal slot. The reflector and director properties of the tunable parasitic elements are used to tilt the main beam of antenna away from the broadside direction. The antenna achieves continuous beam scanning from θ = 0° to 34° for φ = 45°, 90°, 135°, 225°, 270° and 315° planes. The advantage of the antenna is that the design is simple and it maintains a common impedance bandwidth from 2.42–2.47 GHz in all configurations. The two-dimensional beam scanning capability of the proposed antenna can be effectively used in the next generation wireless communication networks.