Pravin Mane

Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)

Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit (MPU). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory-the transpose memory, which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 × faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2×) and energy (10×), with similar area.

Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems

Today in sub-nanometer regime, chip/system designers add accuracy as a new constraint to optimize Latency-Power-Area (LPA) metrics. In this paper, we present a new power and area-efficient Approximate Wallace Tree Multiplier (AWTM) for error-tolerant applications. We propose a bit-width aware approximate multiplication algorithm for optimal design of our multiplier. We employ a carry-in prediction method to reduce the critical path. It is further augmented with hardware efficient precomputation of carry-in. We also optimize our multiplier design for latency, power and area using Wallace trees. Accuracy as well as LPA design metrics are used to evaluate our approximate multiplier designs of different bit-widths, i.e. 4 × 4, 8 × 8 and 16 × 16. The simulation results show that we obtain a mean accuracy of 99.85% to 99.965%. Single cycle implementation of AWTM gives almost 24% reduction in latency. We achieve significant reduction in power and area, i.e. up to 41.96% and 34.49% respectively that clearly demonstrates the merits of our proposed AWTM design. Finally, AWTM is used to perform a real time application on a benchmark image. We obtain up to 39% reduction in power and 30% reduction in area without any loss in image quality.

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82i?area saving, 1.57i?speedup and 3.63i?less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.

ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip

In nanometer regime, optimization of System-on-Chip (SoC) designs w.r.t. speed, power and area is a major concern for VLSI designers today. Imprecise/approximate design obviates the constraints on accuracy, stemming a novel Speed-Power-Accuracy-Area (SPAA) metrics which can pilot to tremendous improvements in speed and/or power with a feeble accord in accuracy. This astonishingly expediency captivated researchers to delve into imprecise/approximate VLSI design evolution. In this paper, we present a new accuracy-configurable multiplier architecture (ACMA) for error-resilient systems. The ACMA uses a technique called Carry-in Prediction for approximate multiplication based on efficient precomputation logic that increases its throughput. The proposed multiplication reduces the latency of an accurate multiplier by almost half by reducing its critical path. The simulation results suggest that SPAA metrics can be administered by exploiting the design for apposite number of iterations. The results for 16-bit multiplication show the mean accuracy of 99.85% to 99.9% in case there is no lower bound on the size of operands and if size of operands are 10-bit or more (numbers > 1000), it results into a mean accuracy of 99.965%.

C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architectures

Mapping of Intellectual Property (IP) cores onto Network-on-Chip (NoC) architectures is a key step in NoC-based designs. Energy, bandwidth, and latency are the key parameters that need to be optimized in such designs. In this paper, we propose Centralized 3-D Mapping (C3Map) using a new octahedral traversal technique and Attractive-Repulsive Particle Swarm Optimization (ARPSO) based algorithms for mapping IP cores onto 3-D NoC architectures. These algorithms efficiently and accurately explore the multi-objective NoC design space. We formulate the IP mapping as minimization of a cost function in order to obtain Pareto optimal IP mappings. We also propose hybridization of ARPSO with known deterministic techniques. We evaluate the proposed C3Map and ARPSO based hybrid algorithms for real-life applications and E3S benchmarks. The experimental results demonstrate the efficiency and effectiveness of C3Map as we achieved significant reduction in communication energy and latency, i.e. 19.51% to 25.81% and 24.15% to 31.21% respectively w.r.t. the known techniques.

Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture

Memristor based nanocrossbar layer fabricated on CMOS layer has shown tremendous potential as high density memory and in reconfigurable logic architectures. Instead of having predesigned Configurable Logic Blocks (CLBs) and memory for reconfiguration as in FPGA, they can be instantiated in nanocrossbar memory as the need arises. We have shown in this paper, the novel design of NOR block as basic unit of computation for in-memory calculations to implement on CMOL FPGA architecture. This block implements its function using material implication. The proposed scheme is against the naturally arising boolean logic based NOR block in CMOL FPGA.

Hybrid CMOS-memristor based FPGA architecture

It is understood that FPGAs suffer in terms of area, performance and power consumption relative to ASICs. With increasing demand for greater density and lower power consumption in memory devices, memristors have emerged as a cutting-edge alternative to transistor based circuitry. The basic issue of static power consumption in routing architecture is solved here as there is no static current flow in memristors; they hold their state when no power is applied. In this paper, a single memory cell based on hybrid technology is designed using TEAM model in memristors. In addition, the design of a configurable logic block (CLB), which can be used to fabricate a hybrid CMOS - Memristor FPGA architecture is explained. The paper also presents an Interconnect design based on hybrid technology which is very easy to design and flexible to program. As the routing architecture is the most important factor determining system speed, this hybrid interconnect could create a new generation of fast and power efficient memristor based FPGAs.

Adder implementation in reconfigurable resistive switching crossbar

Memristors are being investigated by researchers as a replacement for the present non-volatile memory architectures and logical operation units. Such a shift to memristor based devices will allow for the development of computer architectures which are highly advanced than the classical von Neumann architecture. In this paper, we have proposed an N-input stateful-NOR operation on Complementary Resistive Switch (CRS) based crossbar array. The logic is implemented on nanocrossbar arrays where connection and control is provided by underlying CMOS layer. A study of reconfigurable logic using stateful-NOR gate on CRS based crosssbar array and an implementation of 1-bit adder has been presented which has then been extended for N-bit adder. A comparison of 8-bit adder implementation with existing adder architectures on crossbar shows reduction in the number of execution steps required and number of CRS cells used for implementation.

Implicating logic functions with memristors

Conventional FPGAs with SRAM cells, in addition to low density, low speed and higher power consumption, are facing the problems in terms of low retention time due to increase in leakage current as MOS size shrinking continuously due to progress in technology. With the invention and fabrication of memristor as a suitable candidate of 1-bit non-volatile memory, hybrid CMOS-memristor based 3D FPGA architectures have been proposed in literature. In this paper, we propose implication-NOR logic gate based FPGA architecture for implementation of logic functions.

Hybrid CMOS - Memristor based configurable logic block design

With increasing demand for greater storage capacity and lower power consumption in memory devices, memristors have emerged as a cutting-edge alternative to transistor based circuitry. After performing a study of the various models for memristor behavior, the TEAM model was used in this paper because of its flexibility to design a hybrid CMOS-memristor based memory crossbar array. The design is substantiated with appropriate simulation results using Cadence. In addition, a lookup table carrying out the function of 1-bit full adder is implemented as an application of memristor based memory. The paper also presents the design of a configurable logic block (CLB), which can be used to fabricate a hybrid CMOS - Memristor FPGA architecture. Based on the memory design, the study evaluates the various advantages of a memristive device over the traditional CMOS approach and shows that the hybrid memory architecture is more efficient.