C.K. Wang

Drop reliability study of PBGA assemblies with SAC305, SAC105 and SAC105-Ni solder ball on Cu-OSP and ENIG surface finish

Lead free SnAgCu solder joints used in surface mount packages like Ball Grid Array (BGA) have a great impact on the reliability of the end product. The mechanical properties of the solder are important factors. By changing the concentration of silver and copper, or by doping a very low portion of the fourth element (e.g. Ni), the strength of solder can be optimized. In this work, the board-level drop test reliability performance of different PBGA soldered assemblies with three different solder ball alloys (SAC305, SAC105 and SAC 105-Ni200 ppm ) and two surface finishes (Cu-OSP and NiAu) were studied. We found that SAC105-Ni showed the best impact reliability performance among the 3 types of materials, followed by SAC105 and SAC305 for either OSP or NiAu surface finish. OSP surface finish showed better drop lifetime than NiAu surface finish regardless of the type of solder used in the assemblies.

Comprehensive Modeling of Stress-Strain Behavior for Lead-Free Solder Joints under Board-Level Drop Impact Loading Condition

Board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, some drop testing results were summarized based on our previous board-level drop tests. And then the finite element modeling and simulation were conducted to investigate and understand the drop reliability of lead-free solder joints by considering different factors. The strain-rate dependent material properties for lead-free solder has been developed by us and successfully applied in FEA simulation. The important finding of this study is that the constitutive model used has a major impact on dynamic response of solder joint stress and strain results. It was expected that the strain-rate dependent plastic model gave better correlation results than the simple elastic model or bilinear plastic model. In addition to solder material properties, many other factors, including package locations on the PCB, boundary conditions, input-G level, PCB thickness and solder materials, were also simulated to investigate their effects on stress strain performance of solder joint. Comparing to clamped boundary, the 4-screw support condition leads to higher stress level in solder joint. Higher input G-level results in higher solder stress due to larger inertial force and deflection effects on solder joint. The thinner PCB and softer solder can improve the drop performance of board-level electronic assembly.

Cure shrinkage characterization and its implementation into correlation of warpage between simulation and measurement

In this work, a new approach was proposed to characterize the cure shrinkage of EMC by using the EMC/Cu bi-layer strip specimens. The warpage of bi-layer strip was measured at different temperature using Shadow Moire. The results show that warpage at molding temperature was non-zero and zero-warpage temperature shifted from molding temperature (175 degc) to higher temperature due to cure shrinkage effect. From Timoshenkos beam theory, the cure shrinkage was calculated as 1st order approximation theoretically either from the warpage at molding temperature or from zero- warpage temperature. The determined cure shrinkage together with thermal shrinkage obtained from TMA tests was used to predict the warpage of the different EMC/Cu strips. Good correlation was observed in the wide temperature range. As comparison, direct measurement of the cure shrinkage was also done using long rectangular bar specimens. Cure shrinkage was determined by extracting thermal shrinkage from total shrinkage. Cure shrinkage of 2 EMCs were characterized and then applied to PBGA matrix. Warpage of the PBGA EMC/substrate maps was measured using Shadow Moire and simulated as well for the molding compounds (EMCs) after 3 different processes, i.e. after transfer molding (TM), post mold cure (PMC) and PMC + Reflow at 260 degc for 3 times (RF260X3). Consistence between simulation and experiments was found when cure shrinkage was considered. The presented data show the necessity and importance of cure shrinkage in warpage prediction simulation.

Study on the Board-level SMT Assembly and Solder Joint Reliability of Different QFN Packages

The current paper deals with firstly the optimized SMT to assemble various types of QFN (Quad Flat Non- leaded) packages. The important SMT factors such as solder pad and stencil designs will be discussed. Secondly and more importantly, this paper will detail the comprehensive experiment and simulation work done for QFN solder joint reliability modeling. A curve fitted fatigue correlation model together with the use of Schuberts hyperbolic sine lead-free solder constitutive model will be proposed for accurate QFN solder joint reliability prediction.

Development and Assessment of Global-Local Modeling Technique Used in Advanced Microelectronic Packaging

In this study, two types of global-local models are introduced. One is submodeling, in which a coarse global model is used to simulate the whole model and the fine local model is used to simulate the critical region of interest from whole model. The other is global-local-beam (GLB) model, in which the joint is replaced by an equivalent beam with effective stiffness. For submodeling, two different cut boundaries are compared and suitable cut boundary is proposed. In addition, the effective global-local model combining submodeling and GLB modeling technique is also introduced. Case study is presented in this paper. Firstly, PBGA assembly subjected to thermal cycling was investigated using global-local FEA modeling. Secondly, the GLB modeling was used in modal analysis for FCOB assembly. Thirdly, bending simulation was conducted for VQFN assembly using both two-level submodeling and one-level submodeling method.

Development of ball grid array packages with improved thermal performance

To provide electronics packages with sufficient cooling during applications to secure improved reliability and performance of the packages has been one of the challenging tasks for their manufacturers and end users. Since the introduction of the standard ball grid array (BGA) package, continued efforts by package developers have successively resulted in a family of thermally enhanced BGA packages. The extra performance BGA (XP-BGA) package is one of its latest members developed as a cost competitive package for thermal margin. To demonstrate the effectiveness of the XP concept introduced by UTAC, this paper assessed the thermal performance for the two typical BGA families, i.e. FBGA 15times15mm and PBGA 35times35mm, by applying different thermal enhancement methods. Simulation shows that thermal resistance can be reduced by 17% and 25% for XP-FBGA 15times15mm and XP-PBGA 35times35mm respectively at still air comparing with their standard BGA versions. Package thermal performance was observed to improve even more at moving air. Three-dimensional finite volume simulations were further utilized to analyze the impact of several XP related variables on the package thermal performance. XP-FBGA 15times15mm and XP-PBGA 40times40mm multi-chip package (MCP) were selected as test vehicles to study their thermal performance sensitivity to the change of design, materials, process and application environment. The development of XP-BGA achieving thermal performance comparable to that of an EBGA is realized with much lower cost and higher throughput. Package structures, CFD models, and simulation data are presented and discussed

Finite Element Parametric Analysis on Fine-Pitch BGA (FBGA) Packages

Reduction in size of portable products such as cellular phones and camcorders has led to the miniaturization of integrated circuit packages. Fine-pitch BGA (FBGA) packages has been gaining its popularity due to compact in size and relatively low costing. With further down-sizing in package height, reliability issues like die cracking and warpage have surfaced as potential failures. Die cracks results in malfunction of an IC package, while the latter causes difficulty in board surface mounting. In this study, effects of package height on the die stress and warpage have been assessed by FEA. With overmold height ranging from 0.4∼0.6mm and substrate from 0.16∼0.32mm thick, the Overall Package Thickness coding from “T” (1.00<A< = 1.20mm) to “W” (0.65<A< = 0.80mm) are being analyzed. Results revealed that die stress and warpage decreases with increase in overmold thickness. However, an increment in the substrate thickness constituted to a rise in die stress and warpage. It was found that “top clearance” (distance between active die side and package top) of the package contributed to different trends in die stresses. Trends of results in varying the package and die sizes are also being investigated. The findings have provided guidelines for in-house designers in containing possible failures in FBGA packages.Copyright

Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages

IC packages become increasingly complex, which make failure analysis (FA) very challenging. This paper presents advanced packaging failure isolation with time-domain reflectometrv (TDR). where the efforts are put on comparative method investigation. Flip-chip ball grid array (fcBGA) and stacked-die low-profile fine-pitch BGA (stacked-die LFBGA) packages are used to demonstrate advanced packaging FA isolation with TDR and good practices in analysis are highlighted, including signature quality improvement and ground selection. The paper also uses software to mimic and observe TDR signature under various failure modes in order to study TDR behavior with different failure modes. The acquired observations are helpful in packaging FA isolation with TDR.

Thermal performance evaluation and methodology for pyramid stack die packages

The packaging industry has devised various die stacking solutions to meet the electronic industrys growing demand for higher memory and functionality. Multiple devices packaged within the same footprint results in higher temperatures which adversely affect thermal performance and reliability. Thermal management and characterization of stacked die packages thus becomes vital. Thermal evaluation of such packages is complicated as there is more than one heat source. To address this challenge, this paper demonstrates the application of the linear super position (LSP) principle to evaluate the thermal performance of a pyramid stacked die (D2-FBGA) package. The package was modeled using FLOTHERMreg and simulation results were validated with experimental data obtained using JEDEC specified environment and measurement techniques. Upon excellent correlation, an approach using LSP was proposed to generate the thermal resistance matrix used to predict thermal performance for various power configurations. The LSP principle is found to be very suitable for predicting thermal performance of pyramid stack packages with negligible error. This method is very useful for comparing thermal performance of pyramid stacked die packages. To optimize the thermal performance of the package under designed simulation matrix, sensitivity studies of mold compound and die attach conductivity on thermal behavior were also conducted.

Warpage simulation and DOE analysis with application in package-on-package development

The current paper talks about warpage modeling and validation, DOE analysis and approximation model derivation, and solving of actual warpage problem. Warpage of actual PoP (Package-on-Package), both the top and bottom packages, is investigated extensively through modeling and experimental measurement. It is found that the current warpage modeling method using average CTE and linear elastic analysis yields acceptable accuracy. Full factorial DOE analysis using ANSYS, EXCEL and JMP is performed to analyze the impact of design and material on warpage of both bottom and top packages. Surprisingly it is observed from DOE analysis that die size has completely different impact on warpage for top and bottom package. An actual problem, where a PoP top package exhibits large crying mode warpage, is quickly solved with the established warpage analysis method.