Pradeep Lall

Tutorial: temperature as an input to microelectronics-reliability models

This tutorial discusses various modeling methodologies for temperature acceleration of microelectronic-device failures; there are situations in which some methodologies give-misleading results. The aim is to raise the level of understanding of the impact of temperature on reliability and to define the objectives of physics-based temperature modeling. There are alternatives to both the Arrhenius relation and the MilHdbk-217 approach to reliability. In Japan, Taiwan, Singapore, and Malaysia, a physics-of-failure approach is used by most companies. Philips in the Netherlands and the CADMP Alliance in the USA have developed methods and software to conduct physics-based reliability assessments.

Characterization of functional relationship between temperature and microelectronic reliability

Abstract The functional relationship between temperature and microelectronic reliability is presently characterized by an Arrhenius relationship. The Arrhenius relationship encourages lowering temperature to achieve reliability goals. In this paper, the role of temperature in achieving cost-effective reliable electronic equipment has been investigated. The effect of temperature on reliability has been evaluated based on failure mechanisms and electrical parameter variations. The device investigated in this paper is assumed to consist of a bipolar or MOSFET (silicon) semiconductor device with device packaging consisting of first-level interconnects that may be wirebonds, flip-chip, or tape automated bonds, die attachment, substrate attachment, case, lid, lid seal and lead seal. Failure mechanisms actuated under various temperature stresses, including steady-state temperature, temperature cycling, temperature gradients, and time-dependent temperature change, have been identified for each of the package elements. A methodology for derivation of the functional relationship between temperature and microelectronic reliability has been discussed.

A framework for reliability modeling of electronics

The physics-of-failure approach (PoF) to design, reliability modeling, testing and screening of single chip IC packages and multichip modules (MCM), has been developed. The PoF approach is implemented using CADMP-II software. The PoF approach is based on the identification of potential failure mechanisms and failure sites for the product. Failure mechanisms are described by models which characterize the physics of degradation processes leading to failure at each potential failure site. The loads at each failure site are obtained as a function of environmental and operation conditions. The approach preactively incorporates reliability in the design process by establishing a scientific basis for evaluation of new materials, structures, and technologies, through design of tests, screens, safety factors, and acceleration transforms, based on the knowledge of failure mechanisms and modes.

Development of an alternative wire bond test technique

An alternative test technique to the wire bond pull test is presented for wire bond interconnects. The new test technique, based on electromagnetic resonance, has the potential for on-line use as a quality assurance and operational life evaluation method. The new technique greatly reduces the test time in comparison with the existing MIL-STD-883 pull test and internal visual inspection. This new test technique more closely simulates the operational stress than the wire bond pull test and has also shown a sensitivity to defects that would otherwise escape visual inspection. >

Reliability characterization of the SLICC package

SLICC (Slightly Larger than IC Carrier) is a chip-scale ball grid array (BGA) package currently under development at Motorola. The SLICC package consists of a solder-bumped integrated circuit (IC) which is flip-chip bonded to an interposer substrate-approximately 8 mils thick-and then underfilled with an encapsulant. Chip I/Os are routed to package I/Os through plated through holes (PTHs) in the interposer substrate. Package I/Os are composed of solder bumps (approx. 22.2 mils in diameter on a 32-mil pitch) attached to the bottom side of the interposer substrate. The most apparent benefit of the SLICC package is its utilization of the area efficiency associated with direct chip attach (DCA) technology, coupled with the assembly, test, and repair simplicity afforded by BGA-type packaging.

Assembly-level reliability of flex-substrate BGA, elastomer-on-flex packages and 0.5 mm pitch partial array packages

Abstract The assembly-level reliability of the 0.8 mm pitch flex-substrate BGA, 0.65 mm pitch elastomer-on-flex package, and 0.5 mm pitch partial array BGA has been characterized in thermal fatigue, out-of-plane deformation, low frequency repeated bending, and thermal aging. Non-linear finite element models have been used to identify and predict the dominant failure mechanisms and identify the assembly parameters which have a dominant impact on reliability. The model predictions have been verified with accelerated test data. The results have been bench marked against other technologies including 1.5 mm pitch OMPAC TM and 1 mm pitch, 196 I/O Glob-top BGA.

Assembly-level reliability characterization of chip-scale packages

The reliability of the Elastomer-on-Flex Interposer Chip-Scale Package has been studied under thermal fatigue, out-of-plane deformation, humidity and thermal aging. Two versions of the Elastomer-on-Flex Interposer CSP (from a single source) have been characterized in this study-the 48-pin and 40-pin. Both the 40-bump and 48-bump versions have ball 0.3 mm (11.81 mils) in diameter solder balls at 0.75 mm pitch. Non-linear finite element models have been used to identify and predict the dominant failure mechanisms. The model predictions have been verified with accelerated test data. The results for all the dominant failure mechanisms have been bench-marked against existing technologies including overmolded PBGAs and rigid substrate flip-chip BGAs.

Thermomechanical failures in microelectronic interconnects

Abstract Thermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from differences in the coefficients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coefficients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coefficient of expansion, producing significant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect.

Temperature as a Reliability Factor

Many reliability engineers and system designers consider temperature to be a major factor affecting the reliability of electronic equipment. Unfortunately, in an effort to improve reliability, design teams have often lowered temperature without fully understanding the impact on cooling system reliability, in dollars, weight, and size, and the extent of any actual reliability improvement.

A PoF approach to addressing defect-related reliability

This paper discusses using a physics-of-failure (PoF) approach to assessing the defect-related reliability of microelectronic components. Currently, there is no unified approach to some critical questions: What defects, environmental and test or screen loads are the reliability drivers for the device? What magnitudes of defects should be allowed to pass the screens? What is the correlation between the defect magnitudes and operational life? A physics-of-failure approach has been developed to address these concerns and determine screening levels based on failure mechanisms, failure modes, defect magnitudes and environmental stresses for the application. Chosen test and screen levels are unique for each design because they are generated from the physics of the interaction between defects and environmental loads. Some of the potential defects in microelectronic components have been presented. The approach is illustrated by an example application to wire bond interconnects.<<ETX>>