C. Mahata

Atomic layer deposited (TiO2)x(Al2O3)1−x/In0.53Ga0.47As gate stacks for III-V based metal-oxide-semiconductor field-effect transistor applications

Atomic layer deposited (ALD) (TiO2)x(Al2O3)1-x(TiAlO) alloy gate dielectrics on In0.47Ga0.53As/InP substrates are shown to produce high quality interfaces between TiAlO and InGaAs. The surface morphology and interfacial reaction of nanolaminate ALD TiAlO on In0.53Ga0.47As are studied using atomic force microscopy and x-ray photoelectron spectroscopy. Measured valence and conduction band offsets are found to be 2.85 ± 0.05 and 1.25 ± 0.05 eV, respectively. Capacitance-voltage characteristics show low frequency dispersion (∼11%), interface state density (∼4.2 × 1011 cm−2eV−1), and hysteresis voltage (∼90 mV). Ga-O and As-O bonding are found to get suppressed in the gate stacks after post deposition annealing. Our experimental results suggest that higher oxidation states of In and Ga at the In0.53Ga0.47As surface and As diffusion in the dielectric are effectively controlled by Ti incorporation in Al2O3.

Effects of Ti incorporation on the interface properties and band alignment of HfTaOx thin films on sulfur passivated GaAs

Thin HfTaOx and HfTaTiOx gate dielectrics (∼7–8 nm) have been rf sputter-deposited on sulfur passivated GaAs. Our experimental results suggest that the formation of Ga-O at GaAs surface and As diffusion in dielectric may be effectively controlled by Ti incorporation. Possibility of tailoring of band alignment via Ti incorporation is shown. Valence band offsets of 2.6±0.05 and 2.68±0.05 eV and conduction-band offsets of 1.43±0.05 and 1.05±0.05 eV were found for HfTaOx (Eg∼5.45 eV) and HfTaTiOx (Eg∼5.15 eV), respectively.

Impact of Buffer Layer on Atomic Layer Deposited TiAlO Alloy Dielectric Quality for Epitaxial-GaAs/Ge Device Application

The impact of AlGaAs and AlAs buffer layers on the electrical properties of an epitaxial gallium-arsenide (epi-GaAs) metal-oxide-semiconductor capacitor (MOSC) was investigated. MOSC was fabricated by using atomic-layer-deposited Al2O3 -TiO2 (TiAlO) alloy gate dielectric and epi-GaAs layers. The epi-GaAs layer was grown on Ge substrates at 675 °C with and without buffer layer between epi-GaAs layer and Ge substrates. The TiAlO/epi-GaAs interface with an AlGaAs buffer layer allows realizing a high-quality interface between epi-GaAs layers and TiAlO dielectric, much sought after for high-speed transistor applications on a silicon platform. TiAlO dielectric is amorphous even upon annealing at 500 °C and exhibits a sharp interface with epi-GaAs layers. The choice of AlGaAs over AlAs for a buffer layer was made based on the quality of resulting TiAlO/epi-GaAs surface passivation as evident through structural and electrical characteristics. Epi-GaAs with an AlGaAs buffer layer was found to improve the performance of the MOSC significantly through increase in accumulation capacitance and breakdown voltage. The interface state density, flatband voltage, frequency dispersion, and leakage current were decreased for the MOSC fabricated with an AlGaAs buffer layer.

Charge trapping and reliability characteristics of sputtered Y2O3 high-k dielectrics on N- and S-passivated germanium

We demonstrate the potential of sulfur passivation to improve the interface characteristics between germanium (Ge) and Y2O3 high-k gate dielectric. Effects of nitrogen (N) and sulfur (S) passivation of the Ge surface on the charge trapping and reliability properties of Y2O3/Ge gate stacks are studied in detail and the results are compared. Sulfur passivation of the Ge surface has been performed using both the wet sulfidation technique with aqueous ammonium sulfide and plasma sulfidation with H2S gas. N-passivation of Ge substrates has been performed in NO plasma for comparison. Ultrathin (~15 nm) Y2O3 films are deposited on both the N- and S-passivated p-Ge (1 0 0) wafers. Y2O3 films on the S-passivated Ge surface show low fixed oxide charge and interface state density than what is achieved with N-passivation. The electrical characterization results of MOS capacitors with Y2O3 films reveal the potential of S-passivation for the fabrication of Y2O3/Ge gate stacks for Ge MOSFETs.

An extension of the Curie-von Schweidler law for the leakage current decay in MIS structures including progressive breakdown

Abstract The leakage current decay and progressive breakdown in Al/HfYO x /GaAs and Al/Y 2 O 3 /GaAs structures during constant voltage stress are investigated. It is shown that the Curie-von Schweidler law in combination with series and parallel resistances can describe the observed current decrease in these structures accurately. The circuit model incorporates an additional parallel leakage current path associated with the local degradation of the oxide layer as well. Even though the evolution of the current is remarkably different in HfYO x than in Y 2 O 3 because of the applied stress voltage range and current magnitudes, the proposed model is able to capture the main features exhibited by the current–time characteristic in both cases. Experimental data from other authors are analyzed within the same framework.

Thermal stability of HfOxNy gate dielectrics on p-GaAs substrates

The structural, electrical and interfacial properties of metal-oxide–semiconductor (MOS) capacitors with hafnium-oxynitride (HfOxNy) gate dielectrics on p-GaAs substrates were investigated with post-deposition annealing (PDA). X-ray photoelectron spectra (XPS) show the presence of nitrogen at the interface and the intensity increases with annealing temperatures. Although the defective Ga-oxide increases with temperatures, the presence of nitrogen stabilizes and modulates the interface trap by reducing the oxygen vacancy. The electrical characteristics of GaAs MOS devices with HfOxNy gate dielectric show low interface state density, frequency dispersion and hysteresis voltage even after annealing at 600 °C. The accumulation capacitance decreases with annealing temperatures due to the formation of a stable thick nitride interfacial layer. The leakage current density of ~2.4 × 10−6 A cm−2 at VG = −1 V was achieved after 600 °C annealing for an EOT of 3.9 nm. The thermal stability and charge trapping behavior of the HfOxNy/p-GaAs gate stack at a constant voltage and current stressing have exhibited good interface quality and high dielectric reliability, making the films suitable for GaAs-based complementary metal-oxide–semiconductor technology

Internal Photoemission Study on Reliability of Ultra-thin Zirconium Oxide Films on Strained-Si

As scaling laws become less effective in boosting performance for CMOS devices for 90 nm and below, substrate- and process-induced strain engineering are playing an ever increasing role in performance enhancement. Strained-Si MOSFETs are also attractive for high speed and low power applications (Maiti et al., 2007). Ultra thin SiO2 gate dielectrics, of less than 1.5 nm in thickness, are needed for the 45 nm technology node and beyond. In order to reduce the leakage current, an extensive search for alternative high dielectric constant (high-k) gate materials that would probably replace the SiO2 for the sub-45 nm CMOS technologies is being pursued. In this article, we report for the first time, the results of the internal photoemission (IPE) study on reliability properties of microwave-plasma deposited high-k gate dielectric (ZrO2) films on strained-Si/SiGe heterolayers. The kinetics of charge trapping/detrapping and its chemical nature have been investigated through IPE and electron paramagnetic resonance study.

Paramagnetic defects and charge trapping in TaYOx gate dielectrics on strained-Si

Charge trapping kinetics and chemical nature of defects present in Al/TaYOx/strained-Si/Si0.8Ge0.2 MIS capacitors have been studied using internal photoemission and magnetic resonance. Reliability characteristics have been studied using CVS and CCS techniques. Results of electron paramagnetic resonance (EPR) and internal photoemission (IPE) studies on the charge trapping behavior are reported.

Paramagnetic defects and charge trapping behavior of ZrO2 films deposited on germanium by plasma-enhanced CVD

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping behavior and chemical nature of defects in ultrathin (~14 nm) high-k ZrO2 dielectric films deposited on p-Ge (1 0 0) substrates at low temperature (<200 °C) by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma at a pressure of ~65 Pa. Both the band and defect-related electron states have been characterized using electron paramagnetic resonance, internal photoemission, capacitance–voltage and current–voltage measurements under UV illumination. Capacitance–voltage and photocurrent–voltage measurements were used to determine the centroid of oxide charge within the high-k gate stack. The observed shifts in photocurrent response of the Al/ZrO2/GeO2/p-Ge metal–insulator–semiconductor (MIS) capacitors indicate the location of the centroids to be within the ZrO2 dielectric near to the gate electrode. Moreover, the measured flat band voltage and photocurrent shifts also indicate a large density of traps in the dielectric. The impact of plasma nitridation on the interfacial quality of the oxides has been investigated. Different N sources, such as NO and NH3, have been used for nitrogen engineering. Oxynitride samples show a lower defect density and trapping over the non-nitrided samples. The charge trapping and detrapping properties of MIS capacitors under stressing in constant current and voltage modes have been investigated in detail.

Hot carrier degradation in nanowire (NW) FinFETs

Hot carrier reliability of a nanowire Omega-FinFET is investigated for the first time. Hot holes injected into the gate oxide via hot-carrier injection (HCI) at the silicon (Si) - silicon dioxide (SiO2) interface of Omega-FinFETs results in the formation of dangling silicon bonds due to the breaking of silicon-hydrogen bonds and lead to high interface traps generation. The trapping and/or bond breaking creates oxide charge and interface traps affect the Coulomb mobility. A quasi-two dimensional (quasi-2D) physics-based screening Coulomb scattering mobility model has been developed and implemented in Synopsys Sentaurus Device simulator.