Chandan Kumar Sarkar

Introduction to Nano

This books covers the basics of nanotechnology and provides a solid understanding of the subject. Starting from a brush-up of the basic quantum mechanics and materials science, the book helps to gradually build up understanding of the various effects of quantum confinement, optical-electronic properties of nanoparticles, and major nanomaterials. The book covers the various physical, chemical and hybrid methods of nanomaterial synthesis and nanofabrication as well as advanced characterization techniques. It includes chapters on the various applications of nanoscience and nanotechnology. It is written in a simple form, making it useful for students of physical and material sciences.

Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET

Abstract In this paper, the performance of asymmetric underlapped FinFETs (U-FinFETs) is analyzed for linearity and harmonic distortion at high temperatures. The harmonic distortion that arises as a result of non-linear device characteristics requires a detailed analysis for better RF reliability performance. The variations in linearity and distortion characteristics with temperature are analyzed with regards to the primary components of harmonic distortion, second order distortion (HD2), third order distortion (HD3), and the total harmonic distortion (THD). For detailed understanding of the distortion characteristics of U-FinFETs, different device parameters such as the drain current (Ids) and transconductance (gm) are also analyzed. The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonic distortion in the superthreshold regime resulting in better reliability for RF applications.

Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application

This paper represents the energy efficient ultra low power adiabatic sequential logic circuits in sub-threshold regime for the first time in literature. Here, Efficient Charge Recovery Logic (ECRL) based on Differential Cascode Voltage Swing (DCVS) is adopted for the implementation of the circuits to achieve the ultra low power dissipation in sub-threshold regime. Single sinusoidal source is used as supply clock to enjoy the minimal power overheads. In this paper, adiabatic flip-flops and 8 bit Parallel - In - Serial - Out (PISO) shift register have been implemented in sub-threshold regime. Extensive CADENCE simulations for the first time in 22 nm technology node ensure that in sub-threshold regime, ECRL based flip-flops consume only 35% to 45% of total energy consumed by the static CMOS counterpart.

Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application

This paper investigates the low power characteristics of transistor-based adiabatic ECRL logic styles in Sub-threshold regime for the first time in literature. Instead of the multiphase clocking, single clock source is used to enjoy the minimal power overheads. 4-2 Compressor has been implemented to validate the workability of the proposed logic in the sub-threshold regime. A vivid analysis of an 8×8 tree multiplier based on the above mentioned logic also has been implemented. The tree multiplier comprises three sub-circuits: a partial product generator, a partial product compression tree and finally a 16-bit carry look ahead adder. A uniform test bench is set up for fair comparison between the conventional CMOS based tree multiplier and ECRL based tree multiplier circuits to assure the advantage of the proposed logic in terms of power dissipation. Extensive CADENCE simulations have been done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the proposed logic circuit design in sub-threshold regime.

Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance

In this study, the analogue performance of radio-frequency (RF) range amplifiers and ring oscillators designed using fully depleted silicon on insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied for different back oxide (BOX) thickness. The analysis exemplifies the need for BOX thickness variation analysis for the superior analogue/RF performance. The analogue parameters of the circuit analysed for different BOX thickness are the bandwidth, the linearity and the power consumption. The study shows that for an FDSOI MOSFET-based amplifier circuit, with increasing BOX thickness the bandwidth increases and the gain decreases. Also an optimum value of gain–bandwidth product for the amplifier is proposed considering the BOX thickness and the gate length of the device. It is also shown that frequency of oscillation for the ring oscillators increases with increasing BOX thickness.

Applications of Nanotechnology in Next-Generation Nonvolatile Memories

With the conventional MOS Non-Volatile Memory (NVM) devices nearing its limits due to scaling issues; many new devices, advanced structures and materials are being explored for their memory applications. The advanced MOSFET NVMs like the nanocrystal embedded gate dielectric Double Gate (DG) MOS, FinFET and Gate all around (GAA) MOSFET are expected to be integrated in the 3-Dimensional ICs by 2015. Also another class of NVMs which operate based on rather different phenomena than charge trapping (as in MOS devices) has come to the fore in recent years. This new generation of NVMs include the Resistive RAM (RRAM), Ferro FET (FeFET), Spin Torque Transfer (STT)-RAM, CNT/Graphene based memories, CNT mass transport and NEMS NVM etc. Such devices depend on processes like resistive switching, ferroelectric hysteresis, spin-torque transfer and tunneling magnetoresistance modulation, nano manipulation, cantilever actuation and so on. These new NVMs offer considerably faster switching, low power and denser and longer data storage capabilities than the present MOS NVMs. Also the advances in nanofabrication techniques have brought about possibilities of realizing complex multi-layer and 3-D structures with great accuracy. All these developments in materials and design are all set to revolutionize the memory technology. The underlying physics and the quantum effects in such next generation NVM devices are a truly intriguing field of study as well. Various models have been proposed and many new ones are being put forward to study the electron tunneling currents nanocrystal embedded gate advanced MOSFET NVMs, the filament formation mechanisms in RRAM, the spin torque transfer in MRRAM and the various other physical phenomena in such devices. This Chapter provides a comprehensive and up-to date review on the recent developments in the field of NVM devices, discussing new memory devices, architectures and novel data storage mechanisms, with in depth discussions regarding the physics based modeling of such memory cells.

Effect of Ca(OH) 2 , hBN and Mg(OH) 2 based insulators as composite oxides in magnetic tunnel junction memory device properties

Magnetic tunnel junctions (MTJ) have emerged as a possible alternative to charge based data storage cells. With the development in 2-dimensional materials, non-conventional insulators like 2D hexagonal boron nitride (hBN), Ca(OH)2 and Mg(OH)2 have emerged as possible dielectrics in future nanoscale devices. Thus it could be interesting to investigate the application of these materials as insulators in MTJ devices. In this work, we have studied the effect of Ca(OH)2, hBN and Mg(OH)2 based composite oxides in a MTJ device. The barrier height of the composite oxide and effective mass of the same has been calculated using Maxwell-Garnett model. With the MTJ Lab tool available at nanohub, device characteristics were calculated. We have studied various MTJ parameters like parallel and anti-parallel resistance and differential resistance, tunnelling magneto resistance (TMR) and differential TMR (DTMR), and the variation of spin transfer torque (STT) components (In-Plane and Out-of-Plane STT) with voltage.