C.P. Chong

Image-motion detection using analog VLSI

Motion detection by differentiating the output currents of photosensors arranged in a 2D array is described. Subnanoampere current differentiation is made possible by the use of a novel current-mirror (CM) differentiator that requires only four MOSFETs. The pixel density of the motion-detecting imager is higher than 40 pixels/mm/sup 2/. Experimental results of the CM differentiator are reported. >

Sinusoidal oscillators employing current conveyors

The effects of non-zero offset current at terminal z of a current conveyor on the operation of the entire circuit employing it are discussed. Correspondingly, criteria for DC biasing are derived. Application of these criteria leads to a proposal of two new circuits for sinusoidal oscillators. Additional constraints on the value of resistive components required to avoid large DC biasing currents are also considered.

A CMOS current comparator with well-controlled hysteresis

A CMOS current comparator with well-controlled hysteresis is described. The current comparator allows bidirectional input currents. Experimental results show that the current comparator takes approximately 300 ns to resolve a 2 mu A difference of input and threshold currents.<<ETX>>

A novel technique for image-velocity computation

A technique for image-velocity computation is described. Using one set of intersecting delay lines that are physically perpendicular to each other, the two perpendicular components of image velocity can be computed separately if the image area is known. To compute the image velocity without knowledge of the image area, two sets of intersecting delay lines are required. This technique is suitable for analog VLSI implementation. >

Real-time edge detection and image segmentation

The implementation of real-time edge detection and image segmentation using analog VLSI is described. A novel technique of image segmentation using radially propagating signals is discussed. Current-mode processing is used to avoid offset voltages and lead to circuit implementations which are compatible with standard CMOS processes. A system using raylike signal propagation and implemented using 3μ-CMOS technology is described together with experimental results.

The design of a high-resolution CMOS comparator

The authors describe the design of high resolution CMOS comparators by firstly presenting an analysis of comparators with and without the cross-multiplexed technique (XMT). Analytic formulas for the comparison time and the setup time of the comparator are derived. The comparison times calculated are very close to those obtained using SPICE simulation for large coupling capacitances between stages. For small coupling capacitances, the effect of charge-pumping becomes significant and leads to a deviation of the predicted comparison times from those obtained using SPICE simulation. However, the use of XMT, which increases the effective input voltage and thus reduces the charge-pumping effect, leads to a closer agreement between the calculated and simulated comparison times, as well as a significant reduction in the comparison time for cases with small coupling capacitance, where the magnitude of error voltage due to charge pumping is larger. A design example shows that it is possible to implement a CMOS comparator with an input-voltage resolution of less than 100 mu V and a maximum comparison time of less than 2 mu s using XMT.<<ETX>>

An imager with built-in image-velocity computation capability

An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using 3- mu m-CMOS technology is described. Experimental results show that a computational error of less than 20% can be achieved using available fabrication technology. This figure can be reduced by using larger arrays and better implementations of delay gates. >

Using active components to perform voltage division in digital-to-analog conversion

The design of a voltage-mode digital-to-analog (D/A) converter using only fabrication steps required by MOSFETs is described. The converter is implemented using a basic-circuit-building block called the three-input amplifier (TIAMP), which can perform voltage addition and voltage division by 2 without using any passive component. The technique has been used to implement a 12 bit D/A converter for which five samples were tested with accuracies ranging from 6 to 10 bits. Accuracy is limited in the present design by the relatively small sizes chosen for the input transistors. The maximum conversion rate of the present prototypes has been measured to be approximately 1 MHz with a static power dissipation of 50 mW. >

A high-resolution CMOS comparator

A new high-speed high-resolution CMOS comparator is reported in this paper. A new offset-voltage-cancellation technique is used to reduce the effect of clock feed-through or charge pumping. The effective input voltage is doubled by the use of a cross-multiplexed technique. SPICE simulations using a modified MOS3 model (Wong 1986) show that the comparator reported here is capable of resolving 40 μV in less than 2·5 μs and 100μV in 1 μs.

A sub-nanoampere current differentiator

A novel current differentiator capable of differentiating a step current with step size as low as 50 pA is described. It requires only four MOSFETs and consumes less than 10/sup -8/ W power. This makes the novel current differentiator, called the current-mirror (CM) differentiator, a suitable building block for the implementation of motion-detecting imagers with medium pixel density ( approximately=60 pixels/mm/sup 2/). The circuit has been implemented using 3 mu m CMOS technology.<<ETX>>