C.A.T. Salama

Current-mode algorithmic analog-to-digital converters

A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) is presented. The current-mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal. Consequently, the resulting ADCs can be made very small and yet still capable of providing high sampling rates. The advantages and disadvantages of different current mirror structures for use in ADCs are discussed. Experimental results for ADCs fabricated using a 3- mu m CMOS process are reported, including an 8-b ADC which displayed a sampling rate of 500 kHz and a total circuit area of under 0.75 mm/sup 2/. >

Low voltage, high efficiency GaAs Class E power amplifiers for wireless transmitters

A Class E power amplifier for mobile communications is presented. The advantages of Class E over Class B, Class C, and Class F power amplifiers in a low voltage design are discussed. A fully integrated Class E power amplifier module operating at 835 MHz is designed, fabricated, and tested. The circuit is implemented in a self-aligned-gate, depletion mode 0.8-/spl mu/m GaAs MESFET process. The amplifier delivers 24 dBm of power to the 50-/spl Omega/ load with a power added efficiency greater than 50% at a supply voltage of 2.5 V. The power dissipated in the integrated matching networks is 1.5 times the power dissipated in the transistor. >

CMOS wireless phase-shifted transmitter

A fully integrated phase-shifted (PS) transmitter is presented in this paper. The PS transmitter employs switching power amplifiers, operates without mixers, and provides an intermodulation distortion-free output spectrum, making it a suitable choice for mobile communication systems. The RF blocks of the PS transmitter include a local oscillator, phase shifters, and switching class-F power amplifiers with wide-band matching networks. The PS transmitter is implemented in a standard single-polysilicon, six-metal 0.18-/spl mu/m CMOS technology and occupies an area of 3 mm/sup 2/. It operates from a 1-V supply and provides better than 42 dBc adjacent channel power ratio with an output bandwidth of 50 MHz at 8 GHz. The PS transmitter RF front-end provides 22 dBm of average output power with a 38% average power added efficiency.

Image-motion detection using analog VLSI

Motion detection by differentiating the output currents of photosensors arranged in a 2D array is described. Subnanoampere current differentiation is made possible by the use of a novel current-mirror (CM) differentiator that requires only four MOSFETs. The pixel density of the motion-detecting imager is higher than 40 pixels/mm/sup 2/. Experimental results of the CM differentiator are reported. >

Design of submicrometer CMOS differential pass-transistor logic circuits

The interaction between the architectural features of CMOS differential pass-transistor logic (DPTL) and the submicron process technology used to implement it are examined. Techniques that exploit the noise immunity associated with the DPTL architecture are presented to effectively enable signal-swing reductions that result in increased speed. The extent to which DPTL can benefit from this signal-swing/speed tradeoff is examined by investigating the impact of device scaling on DPTL operation. A novel DPTL buffer that enables the implementation of a single-phase clocking scheme and the exchange of signal swing for increased circuit speed is proposed. Experimental results are provided. >

Differential pass-transistor logic

Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTLs fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL.<<ETX>>

Ratio-independent current mode algorithmic analog-to-digital converters

A new ratio-independent algorithmic analog-to-digital converter, using current instead of voltage, is described. The proposed ADC (analog-to-digital converter) does not require well-matched components or high-gain amplifiers and can be made insensitive to the amplifiers offset voltage. A prototype of the proposed circuit was designed and fabricated using a 3- mu m CMOS process. The circuit occupies less than 0.2 mm/sup 2/, displays a 10-b resolution with a 25-kHz sampling rate, and operates from a single 5-V supply.<<ETX>>

A current mode algorithmic analog-to-digital converter

A novel algorithmic analog-to-digital converter (ADC), using current instead of voltage to represent the signal, is described. The use of current eliminates switch-induced errors due to charge injection and results in reasonably high sampling rates without the need for large chip areas. To test this new concept, a 6-bit converter using a 3- mu m CMOS process was fabricated. The resulting circuit occupies a sampling rate of 200 kHz while drawing only 5 mW from a single 5-V supply. The speed of the ADC was limited by the settling time of the relatively large current mirrors.<<ETX>>

An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology

This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of 3.5 mm/spl times/3.5 mm including pads and exhibits an effective resolution bandwidth of 700 MHz at a sampling rate of 2 Gsample/s. The maximum DNL and INL are 0.5 and 1 LSB, respectively. The ADC dissipates 3.5W (including output buffers) from a 3.3-V power supply.

Dynamic GaAs capacitively coupled domino logic (CCDL)

Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1- mu m GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations. >