C. P. Ravikumar

Efficient implementation of ADPCM codec

The optimization of software for embedded systems has been recognized as a key issue in improving cost as well as performance. Embedded software resides in an on-chip ROM and it is crucial to reduce the size of the software when a system-on-chip implementation is being sought. From the view point of size and run-time performance, it is important to eliminate all the redundancy in the code and use efficient coding. In this paper, we describe our experience in realizing an embedded software implementation of an Adaptive Differential Pulse Code Modulation (ADPCM) algorithm. We show that using both machine-independent and machine-dependent code optimization, we can achieve up to 75% improvement in performance and 35% reduction in size. To further improve the performance, we use hardware-software partitioning which can give an improvement in speed-performance by 54% and a reduction by 18% in size.

Testing interconnects in a system chip

Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The system-on-chip (SOC) technology allows us to integrate on the same chip, most of the electronics on a PCB. However, since an SOC operates at a much higher speed and has a very large packaging density, testing its interconnects is different. For example, one must address the crosstalk faults with chip-level interconnects. Not much literature exists on the topic of testing interconnects in core-based systems. We propose a graph-theoretic framework for the problem and a genetic algorithm for testing core interconnects. Our algorithm addresses the issues of test application time, test area overhead, fault-coverage and test power.

A graph-theoretic approach for register file based synthesis

With the increasing use of register files as storage elements in integrated circuits, the problem of assigning data variables to ports of register files has assumed significance. The assignment involves simultaneous optimization of several cost functions, namely, number of register files, number of registers and access ports per register file, and the interconnect both internal and external to memories. In this paper, we refer to multiplexers, busses, and tristate switches when we refer to interconnect. The objective of this paper is to describe graph-theoretic optimization algorithms for the assignment problem. The allocation system described in this paper (SOUPS) accepts a scheduled data flow graph as input and performs (i) assignment of variables to a minimal number of resisters, (ii) assignments of registers to a minimal number of register files, (iii) assignment of registers to ports of the register files using minimal interconnect within the register files, and (iv) assignment of ports of the register files to terminals of functional modules using minimal interconnect outside the register files. We describe experimental results on several benchmark problems.

Synthesis of testable RTL designs

With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to learn to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.

Efficient implementation of multiple on-chip signature checking

Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection latency since it is not until the signatures are scanned out and compared off-chip that a fault become apparent. Aliasing, which is a fallout of long detection latency, is a serious problem. We have proposed an improved BIST architecture which supports on-chip comparison of multiple signatures to minimize the probability of aliasing and total test time. Also we quantified the aliasing probability of the Multiple On-chip Signature Comparison scheme (MOSC) scheme proposed. In this paper, we describe an efficient implementation of the MOSC test architecture and report results on several benchmark circuits. We describe different optimization methods to reduce the overall test control area.

Simulated annealing for target-oriented partial scan

In this paper, we describe algorithms based on simulated annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximise the coverage of faults that are aborted by a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm based on simulated annealing. The SCOAP testability measure is employed to assess the selection of flip-flops during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC. We discuss the TOPS package and its performance on a number of ISCAS89 benchmarks. We also present a comparative evaluation of the benchmark results.<<ETX>>

Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems

Signature-based techniques are well known for the Built-in Self-test of integrated systems. We propose a novel test architecture which uses a judicious combination of mutual testing and signature testing to achieve low test area overhead, low aliasing probability and low test application time. The proposed architecture is powerful for testing highly concurrent systems in applications such as iterative logic arrays, real-time systems, systolic arrays, and low-latency pipelines which tend to have a large number of functional modules of a similar nature. The use of mutual testing helps in testing “self-loop” modules which cannot be tested using simple signature-based schemes. We provide graph-theoretic optimization algorithms to optimize the test area and test application time of the resulting test architecture.

A novel BIST architecture with built-in self check

We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The BILBO-based BIST architecture, used popularly in application-specific integrated circuits, suffers from two disadvantages. First, the initialization of the BILBO registers and the scanning out of the signatures are slow processes due to the sequential nature of these steps. Second, the test application time an a BILBO-based architecture does not depend on whether or not the circuit is faulty. It is typical to organize the testing procedure into one or more test sessions. In each test session, one or more functional modules are tested by applying pseudo-random test patterns. The responses of the functional modules are compressed into signatures which are captured into signature registers. Since the signature of the circuit is compared outside the chip, the test application must continue irrespective of whether or not a fault was detected in the middle of the testing process. More seriously, aliasing errors may result when a single signature is used and testing continues in spite of one or more faulty responses. The test architecture proposed in this paper is abbe to improve the above situation by performing on-chip signature check. Thus, we allow testing and signature comparison to occur concurrently. We show that such a test method can give rise to significant reduction in test application time.

Synthesis of testable pipelined datapaths using genetic search

In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register binding. An initial population of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the schedule and latency information. The operation-to-module binding and the value-to-register binding are then carried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds area-optimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path.

Improving the diagnosability of digital circuits

Testing and fault diagnosis of core-based systems are both difficult problems. Being able to identify which module in the core-based system is faulty has become very important. In this paper, we present algorithms to introduce test points for improving the diagnosability of a digital system. We define a measure of diagnosability known as module resolution which relates to the number of circuit modules that are suspected to be faulty after the diagnostic test procedure has been completed. We present a technique to partition the system into subsystems such that they can be tested in isolation. We also concurrently arrive at a test schedule which minimizes the overall effort in diagnostic testing. We have developed a tool called DEBIT for identifying the number, type, and location of test points in the circuit. We report the results of applying the tool on several benchmark circuits.