C.P. Yue

Physical modeling of spiral inductors on silicon

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance.

A 10-GHz global clock distribution using coupled standing-wave oscillators

In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18-/spl mu/m 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.

Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).

Near speed-of-light signaling over on-chip electrical interconnects

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.

Analysis and optimization of accumulation-mode varactor for RF ICs

This paper presents a novel RF IC varactor implemented in a standard CMOS process. This device has shown a remarkable tuning range of 150%, sensitivity of 300%/V, and quality factor of 23 at 1 GHz. A physical model of the varactor is presented and confirmed with measured data. Using the model derived, optimization has shown that a Q as high as 200 can be achieved.

Modeling and characterization of on-chip transformers

We present a scalable analytical model for on-chip transformers that is suitable for design optimization and circuit simulation. We also provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient (k). The model agrees very well with measurements for a variety of transformer configurations.

A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters

This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters, and 1-bit analog-digital converters. In addition, it includes a low-power phase-locked loop that synthesizes the first local oscillator. The receiver achieves a 2.8-dB noise figure (prelimiter), a 56-dB spurious-free dynamic range, and a 17-dB signal-to-noise ratio for a noncoherent digital back-end implementation when detecting a signal power of -130 dBm at the radio-frequency input.

Kinetics of copper drift in PECVD dielectrics

We quantified the drift of Cu ions into various PECVD dielectrics by measuring shifts in capacitance-voltage behavior after subjecting Cu-gate MOS capacitors to bias-temperature stress. At a field of 1.0 MV/cm and temperature of 100/spl deg/C, Cu ions drift readily into PECVD oxide with a projected accumulation of 2.7/spl times/10/sup 13/ ions/cm/sup 2/ after 10 years. However, in PECVD oxynitride, the projected accumulation under the same conditions is only 2.3/spl times/10/sup 10/ ions/cm/sup 2/. These findings demonstrate the necessity of integrating drift barriers, such as PECVD oxynitride layers, in Cu interconnection systems to ensure threshold stability of parasitic field n-MOS devices.

On-chip RF isolation techniques

On-chip isolation is a function of many interdependent variables. This paper uses industry examples to highlight the isolation impacts of technology - substrate doping levels and triple wells, grounding/guard rings, shielding, capacitive decoupling, and package inductance.

Analysis and synthesis of on-chip spiral inductors

This paper presents a physically based compact model for estimating high-frequency performance of spiral inductors. The model accurately accounts for skin and proximity effects in the metal conductors as well as eddy current losses in the substrate. The model shows excellent agreement with measured data mostly within 10% across a variety of inductor geometries and substrate dopings up to 20 GHz. A web-based spiral inductor synthesis and analysis tool COILS, which makes use of the compact models, is presented. An optimization algorithm using binary searches speeds up the synthesis of inductor designs.