Johnny K. O. Sin

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFTs.

Optimization of the specific on-resistance of the COOLMOS/sup TM/

The optimized values for the physical and geometrical parameters of the p- and n-regions used in the voltage-sustaining layer of the COOLMOS/sup TM/ are presented. Design of the parameters is aimed to produce the lowest specific on-resistance, R/sub on/ for a given breakdown voltage, V/sub B/. A new relationship between the R/sub on/ and V/sub B/ for the COOLMOS/sup TM/ is developed as R/sub on/=C/spl middot/V/sub B//sup 1.32/, where the constant C is dependent on the cell dimension and pattern geometry. It is also found that by putting a thin layer of insulator between the p-region and its neighboring n-regions, the value of R/sub on/ can be further reduced. The possibility of incorporating the insulating layer may open up opportunities for practical implementation of the COOLMOS/sup TM/ for volume production.

A TaN-HfO/sub 2/-Ge pMOSFET with NovelSiH/sub 4/ surface passivation

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ surface annealing prior to HfO/sub 2/ deposition. By using SiH/sub 4/ passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO/sub 2/ Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a /spl sim/140% higher peak mobility than that of the device with surface nitridation.

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

An improved TMAH Si-etching solution without attacking exposed aluminum

In this paper, an improved Tetramethyl Ammonium Hydroxide (TMAH) etching method is reported. The process features higher silicon etching rate and results in smooth silicon surface and at the same time, no significant aluminum etching is observed. We believe that after TMAH etching the aluminum surface is protected by the coating of by-products, which prevents etching of the underlying aluminum films by the TMAH solution. The etchant used in the study consists of 5 wt.% TMAH solution, 1.4 wt.% (or above) dissolved silicon, and 0.4-0.7 wt.% (NH/sub 4/)/sub 2/S/sub 2/O/sub 8/ oxidant additive. Silicon etching rate of 0.9-1.0 /spl mu/m/min and zero aluminum etching rate is be achieved using the process. Moreover the silicon surface remains smooth after etching. The etching process demonstration in this work is readily applicable to MEMS device fabrication such as polysilicon like sacrificial layer removal after metallization is completed.

Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass

A novel low temperature poly-Si (LTPS) TFT technology called the ultra-thin elevated channel TFT (UT-ECTFT) technology is proposed. The devices fabricated using this technology have an ultra-thin channel region (300 /spl Aring/) and a thick drain/source region (3000 /spl Aring/). The ultra-thin channel region is connected to the heavily doped thick drain/source region through a lightly doped overlapped region. The ultra-thin channel region is used to obtain a low grain-boundary trap density in the channel, and the overlapped lightly doped region provides an effective way for electric field spreading at the drain, thereby reducing the electric field there significantly. With the low grain-boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are obtained in the UT-ECTFT. Moreover, this technology provides complementary LTPS TFTs with more than two times increase in on-current and 3.5 times reduction in off-current compared to conventional thick channel LTPS TFTs.

An integrated gas sensor technology using surface micro-machining

We report the silicon based integrated gas sensor technology using surface micro-machined micro-hotplate. Using this technology, an integrated gas sensor sensitive to 1 ppm of carbon monoxide was demonstrated. This approach was extended to integrated gas sensor array application.

Thermal analysis and design of a micro-hotplate for integrated gas-sensor applications

Abstract The application of commercial mechanical computer-aided engineering (MCAE) software to the design and analysis of micro-hotplate (MHP) structures is presented. The simulation provides an estimation of heating efficiency and temperature distribution on the hotplate. The analysis is applied to a newly proposed MHP structure during layout design. Novel design results in a hotplate with high heating efficiency, good temperature uniformity and ease of temperature sensing. The simulation result has been compared with experimental measurement. For the first time, liquid crystal thermography is used to visualize the temperature profile on the hotplate.

Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.