C.R. Cleavelin

Quantum-mechanical effects in trigate SOI MOSFETs

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

In this letter, it is shown that for fin widths down to < 20 nm, strain can be retained in patterned strained-silicon-on-insulator (sSOI) films and is correlated to mobility enhancements observed in FinFET devices. NMOS FinFET mobility is improved by 60% and 30% for [110]/<110> and (100)/<100> fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for [110]/<110> fins, it is enhanced by up to 30% for (100)/<100> fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients.

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

A novel surface-potential based multi-gate FET (MG-FET) compact model has been developed for mixed-signal design applications. For the first time, a MG-FET model captures the effect of finite body doping on the electrical behavior of MG-FETs. A unique field penetration length model has been developed to model the short channel effects in MG-FETs. A multitude of physical effects such as poly-depletion effect and quantum-mechanical effect (QME) have been incorporated. The expressions for terminal currents and charges are co-continuous making the model suitable for mixed-signal design. The model has been verified extensively with TCAD and experimental data.

Radiation Dose Effects in Trigate SOI MOS Transistors

N-channel trigate SOI MOSFETs have been irradiated with 60 Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO2), the current drive reduction in the same devices is 10% if VG=0 V during irradiation and 20% if VG=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO2)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed

Design of FinFET SRAM Cells Using a Statistical Compact Model

A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.

Room-Temperature Low-Dimensional Effects in Pi-Gate SOI MOSFETs

Evidence of a one-dimensional subband formation is found in Pi-gate SOI MOSFETs at room temperature as oscillations are found in the ID(VG) characteristics. These oscillations correspond to an intersubband scattering. Even though the height-to-width ratio of the silicon fins is equal to five, the device behavior is better described by a one-dimensional semiconductor theory than by a two-dimensional gas model

Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices

In this paper we experimentally study for the first time the retention characteristics of Z-RAM cells based on CMOS FinFET and tri-gate devices. A retention time of few milliseconds is measured at room temperature on 100 nm devices. This FinFET based Z-RAM memory will allow manufacturing of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations.