C. Trouiller

Effect of an Organic Inhibitor in High pH Chemical Rinse on the Platen for Cu-CMP

Copper dual damascene has been accepted to be the standard process for sub-quarter microelectronic interconnects. For the process, copper is deposited into an etched pattern by electroplating over a PVD barrier and seed layers. Then, copper chemical mechanical polishing (CuCMP) is used to remove the overburden Cu above the dielectric surface to achieve low topography. Then, the polished wafers are cleaned in order to achieve the minimum density of all kind of particles and impurities, as the final surface cleanliness will directly affect the final yield of the product. Main corrosion issues related to Cu-CMP [i,ii,iii,iv] are chemical corrosion due to uncontrolled copper dissolution, galvanic corrosion due to simultaneous exposure of copper and barrier metal to the slurry; and pattern specific corrosion due to the electrical separation of the lines after CMP and their connection to the devices. In order to prevent such defects, suppression of light during process [2,3], optimization of brush design [4] or addition of corrosion inhibitor in the slurry or the cleaning solution [ii,iii] are reported practices. The most used inhibitor in Cu-CMP chemistries is benzotriazole (BTA). The mechanism of the inhibition of Cu by BTA has been extensively studied in various mixtures and is considered to lower the anodic reaction by the formation of a Cu-BTA complex that can polymerise. The structure and the thickness of this passive film depend on the pH, the BTA concentration, the composition and the redox potential of the solution and the initial oxidation state of the Cu surface[v,vi]. Al-Hinai and Osseo-Asare [vii] showed that the formation of a homogeneous Cu-BTA film during polish is difficult because of the continuous abrasion of the Cu surface compared to nucleation and growth kinetics of film. The resulting Cu surface after the polish is likely covered by a homogeneous passive film. Rinsing the surface with a chemical containing another inhibitor immediately on the platen at a lower downward pressure could be a suitable process to re-inforce the passivation. But, it could significantly increase the organic contamination of the Cu surface. Since these organic Cu complexes are slowly soluble in aqueous solutions, their removal in the subsequent clean can generate carbon particles by redeposition. Although these defects may have little or no direct impact on yield, they often mask more important defectivity issues. In this study, the addition after polish of a wafer rinse containing an organic inhibitor in a high pH chemical was examined. The change in complexation and oxidation of the Cu surface was characterized using TOF-SIMS and completed by defect analysis on 120 and 90 nm products.

Elimination of Post Cu-CMP Watermark by Optimizing Post CMP Clean to Control Cu Dissolution

No watermarks are detected for 1000A of initial cap thickness. Between 400 and 600 A, the density of watermark is multiplied by a factor 10. The increase in watermark with the decrease of the initial cap thickness is explained by a larger low-k film area exposure. In particular, patterned structures with higher metal density will be more eroded because of the increased amount of in-between metal lines dielectric consumption. Auger analysis of the watermark indicates that defects consist of Cu precipitate likely originating from the post-CMP clean step.

In-line TEM sample preparation and wafer return strategy for rapid yield learning

Full wafer dual beam FIB-SEM systems have received a lot of industrial interest in the last years and by now are operational in several 200mm and 300mm fabs. These tools offer a 3D-physical characterization capability of defects and device structures and as such allow for more rapid yield learning and increased process control. Moreover, if SEM resolution is insufficient to reveal defect origin or the necessary process details, it is now also possible to prepare TEM samples using a controlled, easy to learn in-situ process and to efficiently continue the characterization with a high resolution TEM inspection. Thanks to latest hardware developments and the high degree of automation of this TEM sample preparation process, wafers no longer need to be broken and remain essentially free from contamination. Hence, the TEM lamella process can be considered as non-destructive and wafers may continue the fabrication process flow. In this paper we examine the SEM and TEM application capabilities offered by in-line dual beam systems. To qualify the wafer return strategy, the particle contamination generated by the system hardware as well as the process-induced contamination have been investigated. The particle levels measured are fully acceptable to adopt the wafer return strategy. Ga-contamination does exist but is sufficiently low and localized so that the wafer return strategy can be applied safely in the back-end of line process. Yield analysis has confirmed that there is no measurable impact on device yield. Although yet to be proven for the frond-end of line processes, the wafer return strategy has been demonstrated as a valuable one already in the backend of line processes. The as developed non-destructive 3-D SEM-TEM characterization capability does offer value added data that allow to determine the root cause of critical process defects in almost real-time and this for both standard (SEM) and more advanced (TEM) technologies.

Copper Surface Analysis with ToF-SIMS: Spectra Interpretation and Stability Issues

In integrated circuit manufacturing, surface cleanliness is mandatory to achieve high production volumes and device yield. Time-Of-Flight Mass Spectroscopy (ToF-SIMS) is an attractive technique for contamination control since it does provide information about both elemental and molecular species present on essentially any surface and offers high chemical sensitivity associated with sub-micrometer range spatial resolution and short acquisition time. The benefits of this technique to control surfaces after post copper chemical mechanical polishing (Cu-CMP) cleaning [1, 2] and after post via etch cleaning have already been reported.

Influence of the process conditions of a polishing rinse after CuCMP

Immediately after the CuCMP is completed, a polishing rinse is performed in order to remove abrasive of the slurry from the pad and wafer surfaces. The composition of the chemical used for this polishing rinse was demonstrated by Homma et al [1] to be determinant for the prevention of various corrosion defects. In this study, we propose to explore the influence of the process conditions (rinse time, polishing pressure and relative pad sliding velocity) during a polishing rinse on material removal rate, defectivity, electrical performance and surface chemical states. In parallel, the duration of the transition period where the remaining slurry on the pad is influencing the polishing rinse will be determined and its influence will be discussed.

The Role of a Physical Analysis Laboratory in a 300 mm IC Development and Manufacturing Centre

To remain competitive IC manufacturers have to accelerate the development of most advanced (CMOS) technology and to deliver high yielding products with best cycle times and at a competitive pricing. With the increase of technology complexity, also the need for physical characterization support increases, however many of the existing techniques are no longer adequate to effectively support the 65–45 nm technology node developments. New and improved techniques are definitely needed to better characterize the often marginal processes, but these should not significantly impact fabrication costs or cycle time. Hence, characterization and metrology challenges in state‐of‐the‐art IC manufacturing are both of technical and economical nature. TEM microscopy is needed for high quality, high volume analytical support but several physical and practical hurdles have to be taken. The success rate of FIB‐SEM based failure analysis drops as defects often are too small to be detected and fault isolation becomes more difficult in the nano‐scale device structures. To remain effective and efficient, SEM and OBIRCH techniques have to be improved or complemented with other more effective methods. Chemical analysis of novel materials and critical interfaces requires improvements in the field of e.g. SIMS, ToF‐SIMS. Techniques that previously were only used sporadically, like EBSD and XRD, have become a ‘must’ to properly support backend process development. At the bright side, thanks to major technical advances, techniques that previously were practiced at laboratory level only now can be used effectively for at‐line fab metrology: Voltage Contrast based defectivity control, XPS based gate dielectric metrology and XRD based control of copper metallization processes are practical examples. In this paper capabilities and shortcomings of several techniques and corresponding equipment are presented with practical illustrations of use in our Crolles facilities.

ToF‐SIMS Applications in Microelectronics: Quantification of Organic Surface Contamination

An overview of our main Time‐Of‐Flight Secondary Ion Mass Spectroscopy (ToF‐SIMS) applications is first given that highlights the strengths but also reveals some development needs for this technique especially where it comes to contaminants quantification. In this work, as a step towards better quantified data, we have elaborated a method to quantify Airborne Molecular Contamination (AMC) on Silicon. For this a protocol using liquid nitrogen sample cooling was set up to reduce the desorption of the most volatile species under the Ultra High Vacuum (UHV) of the ToF‐SIMS analysis chamber and thus to enable a more stable, reliable and representative measurement. Using this protocol for the ToF‐SIMS analysis and a careful analytical sequence, good correlation between Wafer Thermal Desorption Gas Chromatography Mass Spectroscopy (W‐TDGCMS) and ToF‐SIMS results on wafers exposed for varying time under the clean‐room air flow containing 2,2,4‐trimethyl 1,3‐pentanediol diisobutyrate (TXIB) and Phthalates — two ma...

New photo-acoustic techniques for improved in-line control of opaque metal film processing

In today’s device fabrication the opaque metal film control is generally limited to full-sheet, single layer measurements on monitor wafers since the commonly used techniques require surfaces largely exceeding the typical device dimensions and cannot distinguish multiple layers in a stack. This indirect control method is apart from being expensive and time consuming- not adequate to ensure accurate process control since sampling rates are low and device related process fluctuations remain essentially undetected. Furthermore, for the novel metallization schemes based on damascene structures, the current monitoring is not at all adapted since the final metal thickness obtained after CMP is largely dependent on the device geometry and pattern density. With the introduction of new measurement techniques based on photo-acoustic principles, a new monitoring strategy can be engineered that allows a better and more efficient in-line process control.