C. Vennila

Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio

Cognitive Radio is an application in which Spectrum utilization can be improved by allowing secondary users to use the spectrum when it is not used by licensed primary users. An adaptive OFDM system for Cognitive radio has the ability to nullify unnecessary individual carriers and avoid interference to licensed primary users. A Fast Fourier Transform (FFT) block forms the core of OFDM design. But, the zero valued inputs outnumber the non-zero valued inputs in the FFT block making the standard FFT algorithms computationally inefficient due to wasted operation on zero values. To overcome this problem, several pruning algorithms have been developed. But many of them are architecturally inefficient for FPGA implementation due to complexity of the overhead operations. Moreover, these algorithms are not suitable for applications like Cognitive radio which has zero inputs in arbitrary distributions making hardware implementation to be complex. This paper presents a novel and efficient dynamically partial reconfigurable (DPR) Transform Decomposition (TD) FFT and Radix 2 based IFFT pruning for OFDM based Cognitive Radio on FPGA. Tested FPGA results on XC2VP30 for the DPR method show the configuration time improvement, good area and power efficiency.

Dynamic partial reconfigurable adaptive transceiver for OFDM based cognitive radio

In this paper, we present the implementation and benefits of using dynamic partial reconfigurable adaptive transceiver built for OFDM based Cognitive radio. Determining the appropriate radio communication parameter for a given dynamic channel environment is the primary feature of cognitive radio systems and they are further challenged due to the peak power effect that results from the vectorial addition of the voltage waveforms of each individual carrier. So, we have to select the optimum modulation scheme to get low value of PAPR and to minimize the bit error rate. This paper has undertaken a simulation of a basic transmitter-receiver in a cognitive radio system, and the configuration controller is a look up table based , will learn about the channel environment and be able to provide the appropriate modulation which should be used for the current scenario by taking the expected signal-to-noise ratio (in dB) as input of the transmission.

Dynamic partial reconfigurable Viterbi decoder for wireless standards

In this paper, a high speed and low power runtime dynamically reconfigurable Viterbi decoder architecture with constraint lengths 3-7 with different code rates is proposed for different wireless standards. The proposed architecture uses an improved modular implementation of Add Compare Select (ACS) and Trace back units to obtain high speed. With a throughput of 81Mbps, the architecture is suitable for use in receivers of 802.11a wireless local area network, 3G cellular code division multiple access environments, UMTS and EDGE. The proposed architecture gives high performance without any pipelining or parallelism in ACS and shows at least 13% throughput and 5x power improvement over the reported architectures. To verify the efficacy of this dynamic partial reconfigurable (DPR) Viterbi decoder method, a conventional multiplexer based reconfigurable architecture was designed and tested. DPR based technique shows 27% of resource saving and the reconfiguration time is reduced about 1/9 compared to the static reconfiguration.

Design of Reconfigurable UWB Transmitter to Implement Multi-rate MB-OFDM UWB Wireless System

Abstract-Dynamic and partial reconfiguration allows efficient resource exploitation by configuring tasks on demand and may lead to a decreased chip size, which reduces the static power consumption and can be used in adaptive systems. These systems are able to adapt themselves to the demand of their environment during run-time. The benefit of using dynamic reconfiguration is the possibility to use smaller FPGAs by outsourcing configuration data. This flexibility can be used for many wireless applications. In this paper, a novel Ultra Wide Band (UWB) transmitter is reconfigured to implement multirate MB-OFDM UWB wireless system. In order to prove the efficacy of this approach, a UWB transmitter was designed with a reprogrammable puncturer supporting seven different data rates to demonstrate the practical use of partial reconfiguration technology. The dynamic reconfigurable UWB transmitter proposed in this paper consumes comparatively minimum FPGA resources than the conventional static reconfiguration. Reconfiguration latency is also minimum since the dynamic reconfigurable module taken in this work consumes only 15 slices and successfully implemented on XILINX Virtex II Pro XC2VP30.

Systolic array multiplier for augmenting data center networks communication link

The paper will present a heuristic architecture that is used for the systolic array multiplier for the delay and power—the delay product minimization using various input bit sizes. Systolic architecture maps high-level computation into hardware structures. As these have regularity and can be easily reckoned, the systolic systems are easy to implement. This architecture results in cost effective, better performance and special purpose systems that can solve a wide variety of problems. An effective method for designing Very Large Scale Integration (VLSI) architecture that is based on the proper decomposition technique that uses circular correlations has been presented. Here the multiplication is a commonly used operation in both Mathematics and also in Digital Signal Processing applications. The Systolic algorithm will be an efficient algorithm that performs binary multiplication and the Systolic architectures will provide better performance in design like that of the multiplier, matrix multiplication, the Finite Impulse Response based filter and also the Distributed Array Arithmetic. This work proposed a VLSI architecture based on systolic multiplier that can be implemented on Network links to reduce energy consumption. The proposed work concentrate on the development of a novel architecture having decomposition cells used for the systolic multiplier. There are two different architectures that are proposed and among them the Architecture-I has been designed having the decomposition cells along with registers in case of the feed forward path delay for the delay minimization. This proposed work has resulted in the delay reduction of about 32% that is compared to the existing work. In the architecture-II and their Processing Elements that have been designed along with the tristate buffers and also the multiplexer that is based on the full adder in power minimization. Their results in a lower power delay based product of about 6% compared to the current work and the Field Programmable Gate Array tested proved the delay and the improvement of power-delay product compared to other conventional architectures.

Survey over on-chip buses for VLSI Architecture with optimized delay for multiprocessor system design

In VLSI system design speed, area, and power are the three parameters playing a vital role. Among them the speed is purely determined by the delay taken by the design for its processing. In the delay, the design delay is mainly decided by gate delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more towards the design delay. Because of scaling down in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay or desired speed of the design. In this paper, various on chip buses used for VLSI Architecture for multi processor system design were surveyed in intention with delay optimization towards system design.

Novelty in architecture of ROBDD for the minimization of interconnect delay

In VLSI design of system configuration, three parameters are of major important. Among these three parameters speed, area and power the speed is dependent on the delay of the system. In high speed system design the design delay is contributed by interconnect delay which is the connecting delay of various modules (nodes) i.e. Integrated Protocol. Because of scaling down in the design of high speed system, it is essential to concentrate more towards interconnect delay of the system design to get the optimized delay. Two- level and Multi-level logic minimization is a major problem in logic synthesis and also has the application in modeling in the stages of placement and routing, in fault modeling and in verification of combinational and sequential circuits. Binary Decision Diagram (BDD) is a well-known and widely used in logic synthesis and formal verification of integrated circuits. In this paper various structures of Binary Decision Diagram was studied and experimented to justify the reduction in interconnect delay.