C. Vu

OpenPET: A flexible electronics system for radiotracer imaging

We present the design for OpenPET, an electronics readout system designed for prototype radiotracer imaging instruments. The critical requirements are that it has sufficient performance, channel count, channel density, and power consumption to service a complete camera, and yet be simple, flexible, and customizable enough to be used with almost any detector or camera design. An important feature of this system is that each analog input is processed independently. Each input can be configured to accept signals of either polarity as well as either differential or ground referenced signals. Each signal is digitized by a continuously sampled ADC, which is processed by an FPGA to extract pulse height information. A leading edge discriminator creates a timing edge that is “time stamped” by a TDC implemented inside the FPGA. This digital information from each channel is sent to an FPGA that services 16 analog channels, and information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc. As all of this processing is controlled by firmware and software, it can be modified/customized easily. The system is open source, meaning that all technical data (specifications, schematics and board layout files, source code, and instructions) will be publicly available.

A Readout system for the STAR time projection chamber

We describe the readout electronics for the STAR Time Projection Chamber. The system is made up of 136,608 channels of waveform digitizer, each sampling 512 time samples at 6–12 Mega-samples per second. The noise level is about 1000 electrons, and the dynamic range is 800:1, allowing for good energy loss (dE/dx) measurement for particles with energy losses up to 40 times minimum ionizing. The system is functioning well, with more than 99% of the channels working within specifications.

Front end electronics for the STAR TPC

The Solenoidal Tracker at RHIC (STAR) is a large acceptance detector now being built to study high energy heavy ion collisions. It detects charged particles with a large time projection chamber. The 136,600 TPC pads are instrumented with waveform digitizers, implemented in custom low noise preamplifier/shaper and switched capacitor array/ADCs ICs. The system is highly integrated with all analog functions mounted on small cards that plug into the TPC. Detector mounted readout boards multiplex data from 1152 channels onto a 1.5 Gbit/sec fiber optic link to the data acquisition system.

A monolithic pixel sensor in 0.15μm fully depleted SOI technology

Abstract This letter presents the design of a monolithic pixel sensor with 10 × 10 μ m 2 pixels in OKI 0.15 μ m fully depleted SOI technology and first results of its characterisation. The response of the chip to charged particles has been studied on the 1.35 GeV e - beam at the LBNL ALS.

Design and performance of TPC readout electronics for the NA49 experiment

Abstract Highly integrated readout electronics were developed and produced for the 182000 channels of the four TPCs of the NA49 heavy-ion fixed target experiment at the CERN SPS. The large number of channels, the high packing density and required cost minimization led to the choice of a custom electronics system. The requirements, the design and the performance of the electronics components are described.

ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip

An application-specific integrated circuit (ASIC) wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the Large Hadron Collider. The tester measures values and tolerance ranges of all critical IC parameters, including dc parameters, electronic noise, time resolution, clock levels, and clock timing. The tester is controlled by a field-programmable gate array (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and digital-to-analog converter chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pickup noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.

A low noise amplifier-shaper with tail correction for the STAR detector

A 16 channel low noise amplifier shaper has been designed for the STAR particle detector of the RHIC accelerator. The STAR Amplifier-Shaper (SAS) includes a pole/zero network which cancels the long tail of the Time Projection Chamber (TPC) signal. The tail correction can be adjusted depending on the type of gas used in the TPC. The SAS equivalent noise charge is 900 e/sub RMS//sup -/,, with 25 pf detector capacitance (the test board having 7.7 pF of parasitic capacitance), and with 80 ns shaping time (step response). The measured noise slope is 13.7 e/sub RMS//sup -//pF. The shaper pulse FWHM is adjusted at 180 ns (detector response) with /spl plusmn/4% variation over the entire dynamic range. The shaping time and the tail correction are adjusted with external voltages using MOS resistors. The gain is 16 mV/fC with a linearity of 4%. The crosstalk is about 0.36% which have a negligible effect on the position resolution. The circuit also includes an on-chip calibration system in which the test input charge is controlled by a DC voltage. The output buffer drives a 2 V swing on 50 pF output load for a total power consumption of less than 750 mW (/spl plusmn/5 Volt supply). On-chip protection diodes have also been integrated. The full custom chip has been integrated in the CMOS ORBIT 1.2 /spl mu/m technology with double polysilicon capacitors.

The MAPS based PXL vertex detector for the STAR experiment

The Heavy Flavor Tracker (HFT) was installed in the STAR experiment for the 2014 heavy ion run of RHIC. Designed to improve the vertex resolution and extend the measurement capabilities in the heavy flavor domain, the HFT is composed of three different silicon detectors based on CMOS monolithic active pixels (MAPS), pads and strips respectively, arranged in four concentric cylinders close to the STAR interaction point. The two innermost HFT layers are placed at a radius of 2.7 and 8 cm from the beam line, respectively, and accommodate 400 ultra-thin (50 μ m) high resolution MAPS sensors arranged in 10-sensor ladders to cover a total silicon area of 0.16 m2. Each sensor includes a pixel array of 928 rows and 960 columns with a 20.7 μ m pixel pitch, providing a sensitive area of ~ 3.8 cm2. The architecture is based on a column parallel readout with amplification and correlated double sampling inside each pixel. Each column is terminated with a high precision discriminator, is read out in a rolling shutter mode and the output is processed through an integrated zero suppression logic. The results are stored in two SRAM with ping-pong arrangement for a continuous readout. The sensor features 185.6 μ s readout time and 170 mW/cm2 power dissipation. The detector is air-cooled, allowing a global material budget as low as 0.39% on the inner layer. A novel mechanical approach to detector insertion enables effective installation and integration of the pixel layers within an 8 hour shift during the on-going STAR run.In addition to a detailed description of the detector characteristics, the experience of the first months of data taking will be presented in this paper, with a particular focus on sensor threshold calibration, latch-up protection procedures and general system operations aimed at stabilizing the running conditions. Issues faced during the 2014 run will be discussed together with the implemented solutions. A preliminary analysis of the detector performance meeting the design requirements will be reported.

Sensor Development and Readout Prototyping for the STAR Pixel Detector

The STAR experiment at the Relativistic Heavy Ion Collider (RHIC) is designing a new vertex detector. The purpose of this upgrade detector is to provide high resolution pointing to allow for the direct topological reconstruction of heavy flavor decays such as the D{sup 0} by finding vertices displaced from the collision vertex by greater than 60 microns. We are using Monolithic Active Pixel Sensor (MAPS) as the sensor technology and have a coupled sensor development and readout system plan that leads to a final detector with a <200 {micro}s integration time, 400 M pixels and a coverage of -1 < {eta} < 1. We present our coupled sensor and readout development plan and the status of the prototyping work that has been accomplished.

High-performance electronics for time-of-flight PET systems

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASICs CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASICs CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr3 crystals respectively.