Naresh K. Sehgal

A general approach for regularity extraction in datapath circuits

In the majority of high performance custom IC designs, designers take advantage of the high degree of regularity present in circuits to generate efficient layouts in terms of area and performance as well as to reduce the design effort. We present a general and comprehensive approach to extract functional regularity for datapath circuits from their behavioral or structural HDL descriptions. The fundamental step is the generation of a large set of templates, where a template is a subcircuit with multiple instances in the circuit. Two novel template generation algorithms are presented-one for templates with a tree structure, and the other for a special class of multi output templates, called single principal output (single-PO) templates, where all outputs of a template are in the transitive fanin of a particular output. The set of templates generated is complete under a few simplifying, yet practical, assumptions. This is key to obtaining a desirable cover of the circuit using templates. We show that excellent covers are obtained for various circuits, including ISCAS benchmarks. We also demonstrate that the regularity extracted for these circuits can be used to understand their underlying structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general purpose microprocessors.

A cross section of the issues and research activities related to both information security and cloud computing

Cloud computing amplifies computer security issues that have proliferated with the growth of the Internet. A broad range of security research is being applied to cloud computing. This paper gives a description of cloud computing followed by a general description of information security issues and solutions, and a brief description of issues linking cloud computing with information security. Security solutions must make a trade-off between the amount of security and its performance cost and impact on the end-user experiences. This is accentuated in a cloud computing environment where users desiring different levels of security share the same resources. An essential issue for cloud computing is the perception of security, which is beyond the simple technical details of security solutions. This paper includes a list of a few keyinformation security challenges that also present significant research opportunities. Solving these key problems will encourage the widespread adoption of cloud computing.

Extraction of functional regularity in datapath circuits

Datapath circuits exhibit a very high degree of regularity, which is exploited by designers to generate layouts with a high density and performance as well as to reduce the overall design effort. Regularity in a datapath circuit manifests itself at functional, structural, and topological levels. Functional regularity of a circuit implies the existence of logically equivalent subcircuits-a common feature of datapath circuits. We present a new and comprehensive approach to extract functional regularity for datapath circuits from their high-level or gate-level descriptions. The key step is the generation of a large set of templates, where a template is a subcircuit with multiple instances in the circuit. Two novel template generation algorithms are presented-one for templates with a tree structure, and the other for a special class of multioutput templates, called single-principal-output-graph (SPOG) templates, where all outputs of a template are in the transitive fanin of a particular output. The set of templates generated is shown to be complete under a few simplifying, yet practical, assumptions, which is key in obtaining a desirable cover of the circuit using templates. We present a few extensions to our regularity extraction approach to demonstrate its generality; these extensions include hierarchical representation of regularity and generation of instances of user-specified templates. We show that the generation of the above two classes of templates results in good covers for datapath circuits with a regular bus structure, including several International Conference on Computer-Aided Design benchmark circuits. The regularity extracted from these circuits can be used to easily understand their structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general-purpose microprocessors.

Cloud Workload Characterization

Abstract This paper describes various computer system workloads and relates them to their underlying resource utilization. Specifically, the paper concentrates on Cloud workload characterization based upon issues, capabilities, and technologies surrounding the categories from the multiple points of view of the various players involved in Cloud Computing. The relationship is established between the categories and key limiting underlying technologies, and the dynamic and measurable low-level metrics and measurements that are used to detect and reduce resource contention, and identify category changes during run-time. Research questions are posed on dynamic low-level measurements and a usage case example with high performance computing (HPC) clusters. The Cloud workload categories can provide a basis for common communication for various viewpoints from players, including facility managers, Cloud IT or service providers, Cloud users, consumers, IT managers, and hardware vendors. This common communication tool will facilitate better service-level agreements (SLAs), capital purchase decisions, and future computer architecture design-decisions.

GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs

We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells.

An object-oriented cell library manager

New techniques are proposed to obtain better estimates and optimizations at higher levels of design abstractions, which are then used for library cell selection. A single object-oriented database repository is used during all phases of VLSI design to enhance the early design estimates. As compared to a relational database using sorted tables of attribute values, the proposed object-oriented cell library manager reduces search time for an appropriate cell, with m constraints among n cells, from O(nm) to O(m log n). The proposed method also reduces design cycle time by reducing the number of iterations due to mismatched performance estimates done in the earlier phases of a design.

A gridless multi-layer area router

This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.<<ETX>>

A novel ultra-fast heuristic for VLSI CAD steiner trees

In all stages of VLSI chip design, routing estimation is required to account for the effect of interconnects. We propose a fast Steiner tree construction algorithm, which is 3-180 times faster for 10-300 point Steiner trees, and within 2.5% of the length of the Batched-1-Steiner tree. The proposed method can be used as a fast net length estimation tool in VLSI CAD applications, e.g. in the inner cycle of a floorplanning/placement engine.

Measuring Performance Variability in the Clouds

ABSTRACT Cloud computing is attractive because of its ubiquity and economy of scales. However, there is a wide variability of performance among servers in a public cloud due to virtualization and multiple users sharing the same physical server. Any excessive resource usage by a user will impact other users on the same serve. Performance variability of production cloud services has been reported elsewhere, however, we document hardware resource level performance variations in public clouds. The focus of our study is on the computational capability of a server in a public cloud, and its overall loading level, instead of an end-user applications performance. We will share a study conducted over six different public clouds, with 24 users over a period of three months showing results that present flavours and extent of randomness in the public clouds. Our focus is not limited to any selected workload or user application type, but on the server hardware being deployed and its loading levels by various cloud service providers.

Is the EDA Industry Ready for Cloud Computing

ABSTRACT Many industries are increasingly adopting cloud computing. There are several electronic design automation (EDA) industry players, large and small companies, who have explored the idea of providing cloud-based very large-scale integration design tools and services. This paper briefly explores the history of EDA solutions and their growth path thus far, starting with standalone computer aided design (CAD) tools, through specialized EDA workstations, to integrated suites of tools and flows as currently provided by EDA vendors. A representative EDA flow and its steps are described to provide a basis for relating individual EDA tools to appropriate workload categories. Each step in the EDA design flow is then mapped to a cloud computing workload category. This mapping provides a basis for a decision on moving particular EDA design flow steps to a cloud computing environment. This paper also lists some capabilities currently offered by the public and private cloud providers as a basis for looking at the challenges and opportunities for migrating EDA solutions to cloud computing.