Calliope-Louisa Sotiropoulou

Real-time canny edge detection parallel implementation for FPGAs

Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely contaminated by noise. However, this is a time consuming algorithm and therefore its implementations are difficult to reach real time response speeds. Especially nowadays where the demand for high resolution image processing is constantly increasing, the need for fast and efficient edge detector implementations is ever so present. A new parallel Canny edge detector FPGA implementation is proposed in this paper to answer this demand. This design takes advantage of 4-pixel parallel computations to achieve high throughput without increasing the on-chip memory demands. Synthesis and simulation results are presented to prove the designs efficiency and high frames per second rate.

A Multi-Core FPGA-Based 2D-Clustering Implementation for Real-Time Image Processing

A multi-core FPGA-based 2D-clustering implementation for real-time image processing is presented in this paper. The clustering algorithm is using a moving window technique to reduce the time and data required for the cluster identification process. The implementation is fully generic, with an adjustable detection window size. A fundamental characteristic of the implementation is that multiple clustering cores can be instantiated. Each core can work on a different identification window that processes data of independent “images” in parallel, thus, increasing performance by exploiting more FPGA resources. The algorithm and implementation are developed for the Fast TracKer processor for the trigger upgrade of the ATLAS experiment but their generic design makes them easily adjustable to other demanding image processing applications that require real-time pixel clustering.

Design space exploration for FPGA-based multiprocessing systems

In modern multimedia applications there is a constant increase of the need for more computational power, flexibility and memory availability. The answer for this demand comes from MPSoC platforms implemented on powerful FPGA devices, where high performance and a vast system architecture design flexibility is offered. Whilst many groups are targeting their research on developing automated tools for reducing the total time needed from designing to implementing an MPSoC platform on an FPGA, there is insufficient information on how to explore and determine the optimum memory architecture for such systems. This paper presents a design space exploration for FPGA-based multiprocessing systems using the Powerstone JPEG decoding algorithm as a case study. We explore algorithm partitioning and system architectures for exploitation of both data and task-level parallelism and we include in our study the parameter of different types of memory architectures offered on an FPGA.

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips

A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring on Lab-On-Chips is presented in this paper. The machine vision system is designed to follow continuous or plug flows, for which the menisci of the fluids are always visible. The system discriminates between the front or “head” of the flow and the back or “tail” and is able to follow flows with a maximum speed of 20 mm/sec in circular channels of a diameter of 200 μm (corresponding to approx. 60 μl/sec). It is designed to be part of a complete Point-of-Care system, which will be portable and operate in non-ideal laboratory conditions. Thus, it is able to cope with noise due to lighting conditions and small LoC displacements during the experiment execution. The machine vision system can be used for a variety of LoC devices, without the need for fiducial markers (such as redundancy patterns) for its operation. The underlying application requirements called for a complete hardware implementation. The architecture uses a variety of techniques to improve performance and minimize memory access requirements. The system input is 8 bit grayscale uncompressed video of up to 1 Mpixel resolution. The system uses an operating frequency of 170 Mhz and achieves a computational time of 13.97 ms (worst case), which leads to a throughput of 71.6 fps for 1 Mpixel video resolution.

FPGA-based machine vision implementation for Lab-on-Chip flow detection

This paper presents an FPGA-based machine vision implementation for flow detection on Lab-on-Chip (LoC) experiments. The proposed machine vision system is designed to provide real-time information to the LoC user about the state of the flows (flow coordinates and points of interest) as well as input to the LoC controller. It is uniquely designed to compensate noise in the input video originating from non ideal lighting conditions or LoC movement. This machine vision implementation achieves real time response for input videos of 1Mpixel resolution and frame-rates exceeding 60fps for microfluidic flows with a maximum speed of 20mm/sec.

A multi-core FPGA-based clustering algorithm for real-time image processing

A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The algorithm uses a moving window technique adjustable to the cluster size in order to minimize the FPGA resources required for cluster identification. The window size is generic and application dependent (size/shape of clusters in the input images). A key element of this algorithm is the possibility to instantiate multiple clustering cores working on different windows that can be used in parallel to increase performance exploiting more resources on the FPGA device. In addition to the offered parallelism, the algorithm is executed in a pipeline, thus allowing the cluster readout to be performed in parallel with the cluster identification and the data pre-processing. The algorithm is developed for the Fast Tracker processor for the trigger upgrade of the ATLAS experiment but is easily adjustable to other image processing applications which require real-time pixel clustering.

A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of the single flow implementation on the custom FTK input mezzanine (IM) board are presented. We report on the integration of 16 parallel engines in the same FPGA and the resulting performances. The parallel 2D-clustering implementation has sufficient processing power to meet the specification for the Pixel layers of ATLAS, for up to 80 overlapping pp collisions that correspond to the maximum LHC luminosity planned until 2022.

High-speed FPGA-based flow detection for microfluidic Lab-on-Chip

Machine vision algorithms provide significant benefits for Lab-on-Chip (LoC) systems by automating the experimental process. This paper presents an FPGA-based machine vision flow detection implementation for microfluidic Lab-on-Chip (LoC) experiments. We propose and implement a novel architecture that exploits modern FPGA parallelism capabilities and makes efficient use of device resources to achieve real-time data collection in megapixel resolutions, at rates exceeding 30000 frames per second.

ATCA-based ATLAS FTK input interface system

High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. One of the major challenges is data formatting, where hits from thousands of silicon modules must first be shared and organized into overlapping eta-phi trigger towers. Communication between nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a full mesh backplane is a natural solution. A custom Advanced Telecommunications Computing Architecture data processing board is designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board to board communication channels while keeping the design as simple as possible. We have performed the first prototype board testing and our first attempt at designing the prototype system has proven to be successful. Leveraging the experience we gained through designing, building and testing the prototype board system we are in the final stages of laying out the next generation board, which will be used in the ATLAS Level-2 Fast TracKer as Data Formatter, as well as in the CMS Level-1 tracking trigger R&D for early technical demonstrations.The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker are clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking engines. First, FTK Input Mezzanine cards receive hit data and perform clustering to reduce data volume. Then, the ATCA-based Data Formatter system will organize the trigger tower data, sharing data among boards over full mesh backplanes and optic fibers. The board and system level design concepts and implementation details, as well as the operation experiences from the FTK full-chain testing, will be presented.

A MULTI-CORE FPGA-BASED 2D-CLUSTERING ALGORITHM FOR HIGH-THROUGHPUT DATA INTENSIVE APPLICATIONS

A multi-core FPGA-based clustering algorithm for high-throughput data intensive applications is presented. The algorithm is optimized for data with two dimensional organization (e.g. image processing, pixel detectors for high energy physics experiments etc.). It uses a moving window of generic size to adjust to the application’s processing requirements (the cluster sizes and shapes that appear in the input data sets). One or more windows (cores) can be used to identify clusters in parallel, allowing for versatility to increase performance or reduce the amount of used resources. In addition to the inherent parallelism the algorithm is executed in a pipeline, thus allowing for readout to be performed in parallel with the cluster identification.