Spyridon Nikolaidis

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips

A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring on Lab-On-Chips is presented in this paper. The machine vision system is designed to follow continuous or plug flows, for which the menisci of the fluids are always visible. The system discriminates between the front or “head” of the flow and the back or “tail” and is able to follow flows with a maximum speed of 20 mm/sec in circular channels of a diameter of 200 μm (corresponding to approx. 60 μl/sec). It is designed to be part of a complete Point-of-Care system, which will be portable and operate in non-ideal laboratory conditions. Thus, it is able to cope with noise due to lighting conditions and small LoC displacements during the experiment execution. The machine vision system can be used for a variety of LoC devices, without the need for fiducial markers (such as redundancy patterns) for its operation. The underlying application requirements called for a complete hardware implementation. The architecture uses a variety of techniques to improve performance and minimize memory access requirements. The system input is 8 bit grayscale uncompressed video of up to 1 Mpixel resolution. The system uses an operating frequency of 170 Mhz and achieves a computational time of 13.97 ms (worst case), which leads to a throughput of 71.6 fps for 1 Mpixel video resolution.

FPGA-based machine vision implementation for Lab-on-Chip flow detection

This paper presents an FPGA-based machine vision implementation for flow detection on Lab-on-Chip (LoC) experiments. The proposed machine vision system is designed to provide real-time information to the LoC user about the state of the flows (flow coordinates and points of interest) as well as input to the LoC controller. It is uniquely designed to compensate noise in the input video originating from non ideal lighting conditions or LoC movement. This machine vision implementation achieves real time response for input videos of 1Mpixel resolution and frame-rates exceeding 60fps for microfluidic flows with a maximum speed of 20mm/sec.

A multi-core FPGA-based clustering algorithm for real-time image processing

A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The algorithm uses a moving window technique adjustable to the cluster size in order to minimize the FPGA resources required for cluster identification. The window size is generic and application dependent (size/shape of clusters in the input images). A key element of this algorithm is the possibility to instantiate multiple clustering cores working on different windows that can be used in parallel to increase performance exploiting more resources on the FPGA device. In addition to the offered parallelism, the algorithm is executed in a pipeline, thus allowing the cluster readout to be performed in parallel with the cluster identification and the data pre-processing. The algorithm is developed for the Fast Tracker processor for the trigger upgrade of the ATLAS experiment but is easily adjustable to other image processing applications which require real-time pixel clustering.

A unified CMOS inverter model for planar and FinFET nanoscale technologies

In this paper, a new analytical model for describing the output waveform of the CMOS inverter for planar and FinFET nanoscale technologies, is introduced. A modified expression for the transistor current is adopted taken into account nano-scale effects like DIBL, CLM and NWE. The sub-threshold current of both transistors as well as their drain-to-bulk capacitances, which influence significantly the accuracy, are also considered. Results for 32nm planar and 20nm FinFET technologies validate the proposed model.

Modeling CMOS Gates Using Equivalent Inverters

In this paper a complete approach for timing and power modeling and characterization of the CMOS gates is proposed. At first, a simplified but still accurate transistor current model is proposed taking into account the nanoscale effects which have a countable effect on the circuit behavior. Using the expressions of the transistor current, the differential equation which describes the operation of the CMOS inverter is solved analytically and expressions for the output voltage and supply current and thus for propagation delay and the power consumption are derived. These expressions are parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. Complex gates are replaced by equivalent inverters with similar behavior and the expressions developed for the inverter are employed. Parametric expressions are derived for the transistor widths of the equivalent inverters using a fitting procedure. Results for the NAND and NOR gates show that the proposed approach presents a sufficient accuracy with an average error in propagation delay at 5%.

Static gate power consumption model based on power contributors

Accurate and fast estimation of the static power consumption in various design corners for nanoscale integrated circuits is a very important task since it facilitates power and noise analysis procedures. The power contributor approach which is based on the separability of the power components can be used for this purpose. In this paper, parametric models for the power contributor currents are produced for the cells of an industry oriented library. Using these models, the power contributor method is evaluated for the estimation of the total static power consumption of the library cells. The models produced are expressed as a function of the power supply voltage, temperature and the transistor width. Results show that the proposed model estimations present an average error of about 0.4% while the maximum error remains less than 2% for all the design corners of the tested cells.

A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of the single flow implementation on the custom FTK input mezzanine (IM) board are presented. We report on the integration of 16 parallel engines in the same FPGA and the resulting performances. The parallel 2D-clustering implementation has sufficient processing power to meet the specification for the Pixel layers of ATLAS, for up to 80 overlapping pp collisions that correspond to the maximum LHC luminosity planned until 2022.

High-speed FPGA-based flow detection for microfluidic Lab-on-Chip

Machine vision algorithms provide significant benefits for Lab-on-Chip (LoC) systems by automating the experimental process. This paper presents an FPGA-based machine vision flow detection implementation for microfluidic Lab-on-Chip (LoC) experiments. We propose and implement a novel architecture that exploits modern FPGA parallelism capabilities and makes efficient use of device resources to achieve real-time data collection in megapixel resolutions, at rates exceeding 30000 frames per second.

A data-driven Verilog-A ReRam model

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

A TiO2 ReRAM parameter extraction method

In this work, we present a parameter extraction method for TiO2 memristive devices that applies on a resistive switching rate model which embodies only four parameters for each voltage biasing polarity. The simple form of the model functions allows the derivation of a predictive analytical resistive state response expression under constant bias voltage. By employing corresponding experimental testing on the devices, we fit such constant bias responses exhibited by physical memristor samples on this analytical expression. Next, we apply a simple algorithm that extracts the suitable model parameters that capture the switching rate behavior of the characterized device in its voltage range of operation.