Cam Phu Thi Nguyen

Drain-Induced Barrier Lowering and Parasitic Resistance Induced Instabilities in Short-Channel InSnZnO TFTs

Effect of short-channel induced instabilities in InSnZnO-based thin-film transistors (TFTs) caused by combination of the drain induced barrier lowering (DIBL) and parasitic resistance is reported. As the active channel length decreased below a critical value of around 8 μm, the draincurrent (2.81 μA) are abruptly increased and N-shaped behavior of the transconductance are observed due to the formation of additional current path in the channel. The magnitude of subgap density of states is also depended on the channel size. The higher value of parasitic resistance RSD (~42 kg) and DIBL coefficient (76.8 mV/V) in short-channel ITZO TFT devices are also discussed.

Improvement of Mobility in Oxide-Based Thin Film Transistors: A Brief Review

Copyright ©2015 KIEEME. All rights reserved. This is an open-access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted noncommercial use, distribution, and reproduction in any medium, provided the original work is properly cited. pISSN: 1229-7607 eISSN: 2092-7592 DOI: http://dx.doi.org/10.4313/TEEM.2015.16.5.234 OAK Central: http://central.oak.go.kr

Improved Data Retention of InSnZnO Nonvolatile Memory by H 2 O 2 Treated Al 2 O 3 Tunneling Layer: A Cost-Effective Method

An experiential aspect regarding the improvement of retention characteristics of InSnZnO (ITZO) thin-film transistor-based nonvolatile memory (TFT-NVM) devices with a hydrogen peroxide H₂O₂ treated Aluminum oxide (Al₂O₃) tunneling layer is reported. A better performance in retention of ~92% (after ten years), a smaller subthreshold swing of 96 mV/decade, and a higher field effect mobility of 31.08 cm²/V·s were obtained in H₂O₂ treated TFT-NVM devices compared with untreated one. Furthermore, employing the H₂O₂-treatment in the Al₂O₃ layer provided oxygen-rich (O/Al ratio = 1.45) and OH-residuals free Al₂O₃, which effectively minimized the interface states (1.34 × 1011 cm^-2 eV^-1) between the ITZO/(Al₂O₃/SiOx/SiO₂) stack through strong oxidation. These results suggest that high-quality Al₂O₃ dielectric layer can be obtained through cost-effective H₂O₂ oxidation techniques for TFT-NVM devices.

High performance non-volatile memory with the control of charge trapping states in an amorphous InSnZnO active channel

In this study, the influence of interface states between an indium tin zinc oxide (ITZO) active layer and a gate insulator on memory characteristics was examined as a function of annealing temperature. The annealing nonvolatile memory (NVM) devices have shown the best electrical characteristics such as high field effect mobility (27.22 cm2 V−1 s−1), low threshold voltage (0.15 V), low subthreshold slope (0.17 V dec−1), and high on/off current ratio (7.57 × 107) in comparison with as-deposited devices. By annealing at 250 °C, the number of ITZO/insulator interface trap densities was reduced. The effect of the remaining trap states on the retention characteristic of memory devices is negligible. The performance of NVM devices using different annealing temperatures of ITZO and a multi-stack gate insulator SiO2/SiOx/SiOxNy with Si-rich SiOx for the charge storage layer was also reported. The 250 °C annealed ITZO-based NVM device showed a retention exceeding ~94% of the threshold voltage shift after 104 s and greater than ~90% after 10 years with a low operating voltage of +11 V at only 1 μs programming duration time. Therefore, the NVM devices, which were fabricated by the low ITZO/insulator interface trap densities, were highly suitable for potential application in memory systems.

Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor

We reported the influence of interface trap density (Nt) on the electrical properties of amorphous InSnZnO based thin-film transistors, which were fabricated at different direct-current (DC) magnetron sputtering powers. The device with the smallest Nt of 5.68 × 1011 cm−2 and low resistivity of 1.21 × 10−3 Ωcm exhibited a turn-on voltage (VON) of −3.60 V, a sub-threshold swing (S.S) of 0.16 V/dec and an on-off ratio (ION/IOFF) of ~8 × 108. With increasing Nt, the VON, S.S and ION/IOFF were suppressed to −9.40 V, 0.24 V/dec and 2.59 × 108, respectively. The VTH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices. The result showed that the reduction in Nt contributes to an improvement in the electrical properties and stability.