Cameron D. Patterson

Cognitive Radio and Networking Research at Virginia Tech

More than a dozen Wireless @ Virginia Tech faculty are working to address the broad research agenda of cognitive radio and cognitive networks. Our core research team spans the protocol stack from radio and reconfigurable hardware to communications theory to the networking layer. Our work includes new analysis methods and the development of new software architectures and applications, in addition to work on the core concepts and architectures underlying cognitive radios and cognitive networks. This paper describes these contributions and points towards critical future work that remains to fulfill the promise of cognitive radio. We briefly describe the history of work on cognitive radios and networks at Virginia Tech and then discuss our contributions to the core cognitive processing underlying these systems, focusing on our cognitive engine. We also describe developments that support the cognitive engine and advances in radio technology that provide the flexibility desired in a cognitive radio node. We consider securing and verifying cognitive systems and examine the challenges of expanding the cognitive paradigm up the protocol stack to optimize end-to-end network performance. Lastly, we consider the analysis of cognitive systems using game theory and the application of cognitive techniques to problems in dynamic spectrum sharing and control of multiple-input multiple-output radios.

Wires on Demand: Run-Time Communication Synthesis for Reconfigurable Computing

In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing a variety of datapaths. Our approach allocates a sandbox region in which modules from a library can be flexibly placed and interconnected. An efficient run-time framework makes use of lightweight placement and routing techniques to respond on-demand to application requests. Compile time tools automate the task of adding interface wrappers to modules, insulating the designer from reconfiguration details.

Design and Evaluation of an Active Antenna for a 29–47 MHz Radio Telescope Array

The eight-meter-wavelength transient array (ETA) is a new radio telescope consisting of 12 dual-polarized, 38 MHz-resonant dipole elements which are individually instrumented, digitized, and analyzed in an attempt to detect rare and as-yet undetected single dispersed pulses believed to be associated with certain types of astronomical explosions. This paper presents the design and demonstrated performance of ETAs dipole antennas. An inverted V-shaped design combined with a simple and inexpensive active balun yields sensitivity which is limited only by the external noise generated by the ubiquitous Galactic synchrotron emission over a range greater than the 27-49 MHz design range. The results confirm findings from a recent theoretical analysis, and the techniques described here may have applications in other problems requiring in situ evaluation of large low-frequency antennas

Low-cost and area-efficient FPGA implementations of lattice-based cryptography

The interest in lattice-based cryptography is increasing due to its quantum resistance and its provable security under some worst-case hardness assumptions. As this is a relatively new topic, the search for efficient hardware architectures for lattice-based cryptographic building blocks is still an active area of research. We present area optimizations for the most critical and computationally-intensive operation in lattice-based cryptography: polynomial multiplication with the Number Theoretic Transform (NTT). The proposed methods are implemented on an FPGA for polynomial multiplication over the ideal ℤp[x]〈xn + 1〉. The proposed hardware architectures reduce slice usage, number of utilized memory blocks and total memory accesses by using a simplified address generation, improved memory organization and on-the-fly operand generations. Compared to prior work, with similar performance the proposed hardware architectures can save up to 67% of occupied slices, 80% of used memory blocks and 60% of memory accesses, and can fit into smallest Xilinx Spartan-6 FPGA.

Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

An efficient run-time router for connecting modules in FPGAS

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Rapidly increasing FPGA density and complexity has heightened the need for higher levels of abstraction in validation and more rapid, focused approaches for design inspection. We present two methods of validating and debugging active, implemented FPGA designs running at target speeds. The first binds high-level software reference models directly to hardware enabling complex, automated, software-controlled testing scenarios, reducing the reliance on simulation. The second approach provides direct interactivity and visibility into a running FPGA design, enabling software-controlled breakpoints and arbitrary access to design registers. In-circuit breakpoints can be modified without the need to re-implement the entire design.

JHDLBits: The Merging of Two Worlds

This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a “sandbox” to explore advanced interactions with FPGA bitstreams. This paper presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components – JHDL, JBits3 for Virtex-II, and the ADB connectivity database – are linked together to provide a cohesive design environment.

PATIS: Using partial configuration to improve static FPGA design productivity

Reconfigurable hardware development and debugging tools aspire to provide software-like productivity. A major impediment, however, is the lack of a module linkage capability permitting hardware blocks to be compiled concurrently, limiting the effective use of multi-core and multiprocessor platforms. Although modular and incremental design flows can reuse the layouts of unmodified blocks, non-local changes to the logical hierarchy or physical layout, or addition of debug circuitry, generally force complete re-implementation. We describe the PATIS dynamic floorplanner, targeting development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The floorplan consists of partial modules with structured physical interfaces observable through configuration readback rather than synthesized logic analysis circuitry, allowing module ports to be passively probed without disturbing the layout. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent and concurrent invocations of the standard Xilinx tools running on separate cores or hosts. A continuous background task proactively generates floorplan variants to accelerate global layout changes. The partial reconfiguration design flow is easier to automate in PATIS because run-time module swapping is not required, suggesting that partial reconfiguration may serve a useful role in large-scale static design.

Application-Level Autonomic Hardware to Predict and Preempt Software Attacks on Industrial Control Systems

We mitigate malicious software threats to industrial control systems, not by bolstering perimeter security, but rather by using application-specific configurable hardware to monitor and possibly override software operations in real time at the lowest (I/O pin) level of a system-on-chip platform containing a micro controller augmented with configurable logic. The process specifications, stability-preserving backup controller, and switchover logic are specified and formally verified as C code commonly used in control systems, but synthesized into hardware to resist software reconfiguration attacks. In addition, a copy of the production controller task is optionally implemented in an on-chip, isolated soft processor, connected to a model of the physical process, and accelerated to preview what the controller will attempt to do in the near future. This prediction provides greater assurance that the backup controller can be invoked before the physical process becomes unstable. Adding trusted, application-tailored, software-invisible, autonomic hardware is well-supported in a commercial system-on-chip platform.