Jorge Surís

Wires on Demand: Run-Time Communication Synthesis for Reconfigurable Computing

In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing a variety of datapaths. Our approach allocates a sandbox region in which modules from a library can be flexibly placed and interconnected. An efficient run-time framework makes use of lightweight placement and routing techniques to respond on-demand to application requests. Compile time tools automate the task of adding interface wrappers to modules, insulating the designer from reconfiguration details.

An efficient run-time router for connecting modules in FPGAS

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

Blind signal parameter estimation for the Rapid Radio framework

There are many instances where it is desirable or even essential to rapidly build a functional radio receiver to recover symbols from an unknown modulated source. The term ¿rapid radio¿ refers to a demonstrable analysis environment and receiver implementation methodology for rapid deployment. An automated tool for signal analysis requires several stages for the estimation and classification of the RF signal parameters and modulation type. To fulfill the requirements of the first stage in the case of single carrier linear modulations, an estimator of the symbol rate, frequency offset, and roll-off factor based in frequency-domain analysis is proposed. An estimate of the SNR is obtained as a by-product of the method. The technique was validated with experiments over-the-air.

Slotless module-based reconfiguration of embedded FPGAs

The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking the blocks in a manner that suits each applications unique connectivity, bandwidth, and latency requirements. Our approach uses the standard Xilinx implementation tools to generate dynamic module partial bitstreams, but choosing the modules coordinates and completing connections to other modules are runtime operations. Scripts automatically add interface wrappers to dynamic modules and generate a library of relocatable partial bitstreams. The library is used by an efficient runtime system that completes application requests for instancing and connecting modules, effectively insulating the designer from FPGA reconfiguration complexities. In this way, a large sandbox may be allocated to dynamic modules rather than fixed module slots and interconnect. Application engineers interact with the Wires on Demand (WoD) system through a runtime software API, and do not have to master hardware description languages and implementation tools.

Untethered On-The-Fly Radio Assembly With Wires-On-Demand

In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing datapaths. We present the wires-on-demand framework that allocates a sandbox region in which modules from a library are flexibly placed and interconnected rapidly and autonomously in an embedded platform without vendor tools.

Enhancing the Productivity of Radio Designers with RapidRadio

In this paper the RapidRadio framework for signal classification and receiver deployment is discussed. The frame- work is a productivity enhancing tool that reduces the required knowledge-base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. The framework’s capacity to classify a signal and deploy a functional receiver is validated with over- the-air experiments.

RapidRadio: Signal Classification and Radio Deployment Framework

In this article, the RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity-enhancing tool that reduces the required knowledge base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. RapidRadio divides the process of radio creation into two phases; the analysis phase and radio synthesis phase. The analysis phase guides the user through the process of classifying an unknown signal and determining its modulation scheme and parameters, resulting in a radio receiver model. In the second phase, this model is transformed into a functional receiver in an FPGA-based platform.

On the Implementation of a Quasi-Generic Synchronization Architecture for Linear Digital Modulations

With increasing availability of software-defined radio platforms, users are no longer tied to receiving or transmitting only one type of signal. In applications, such as signal intelligence, the user may not know ahead of time the characteristics of the signal to be received. This uncertainty results in a need for more flexible receiver architectures that can be easily modified to work for multiple signal types. In this paper the FPGA implementation of a quasi-generic synchronization architecture is presented that is easily adaptable, at implementation time, to most linear modulation schemes. The implementation is shown to work for QPSK, 8QAM, 16QAM and 32QAM with timing frequency errors of up to 4% of the symbol rate.

Rapid radio: A framework for human-assisted signal classification and receiver implementation

An analysis-based framework for the rapid development of a radio receiver for signals with unknown parameters is pro-posed, exploiting the reconfiguration capabilities of FPGAs. The framework guides a non-expert user through the process of signal classification and FPGA-based receiver implementation. System efficiency is traded off with implementation time in order to allow fast radio creation. A set of high-level transformations are applied to the unknown signal based on different hypothesis about the modulation scheme. The results of the transformations are presented to the user, who can steer the process of analysis. The parameters of the radio are then mapped by means of an Implementation Engine to modules implemented in a general purpose FPGA-based receiver.

Exploring Non-Traditional Hardware-Software Interaction

The joint test action group (JTAG) has created what has become a world-wide standard/debug interface for a variety of hardware devices. The emergence of devices such as the Xilinx Virtex-II Pro FPGA, which closely couple advanced microprocessors with reconfigurable logic, presents an opportunity to expand JTAGs capabilities beyond debugging. We present the design and implementation of a platform that combines JTAG, reconfigurable logic, and advanced processor debug features to create a rich environment for exploring non-traditional interaction between hardware and software. More specifically, we outline several possible configurations, discuss performance, and present possible applications