Can Baltaci

Thermal issues in deep sub-micron FDSOI circuits

Self-heating effects became more prominent with the introduction of the modern devices like FDSOI and low thermal conductivity materials such as SiO2. Consequently, the design of high speed digital circuits which are the time-critical blocks of high performance processors started to be limited mainly by thermal issues. For observing the thermal behaviour of FDSOI structure on circuit level, a 64-bit Kogge-Stone parallel prefix adder is designed and implemented in 40nm bulk CMOS technology and thermal model of the circuit is extracted and simulated according to FDSOI design parameters. The implemented adder circuit has a critical path delay of 148ps under 900 mV power supply voltage with a power consumption of 12mW. The temperature profile of the designed circuit is extracted with thermal simulations and the peak temperature locations are examined in detail. The hot spot locations and their temperature values are correlated with the power density. It is shown that self-heating of high power density devices has a significant influence on the peak temperature of a design. Finally, a simple design solution is proposed which can significantly decrease the peak temperature.

Design Automation for Differential Circuits

The process of designing semi-custom circuits necessitates the usage of a variety of automation tools. Unfortunately, no existing suite of tools allows to construct circuits with differential cells. Because of this, advantages of differential circuits cannot be exploited efficiently. In this chapter, a design flow will be presented for differential circuits, which provides solutions at different stage for using existing automation tools. The proposed flow attempts to minimize the processing of data, resulting in a trustable implementation.

Analysis of MOS Current-Mode Logic Circuits

In this chapter, an analytical model will be developed for MOS Current-Mode Logic circuits. First, the differential pair will be studied, and a simple and accurate model will be presented, using a transregional modeling approach based on the EKV transistor model. Based on this model, MCML gates are studied, and essential properties and tradeoffs highlighted. Then, the effect of nonlinearities on power supply noise is analyzed. Finally, a model for the effect of random parameter variation is developed and presented.

Design Example III: Grain-128a Stream Cipher

In this chapter, a third design example is presented. The considered circuit is the Grain-128a stream cipher with × 2 option which is a cryptographic block. The circuit is designed in a 180 nm bulk CMOS technology both with MCML and CMOS gates for comparing the power supply noise performance.

Design Example II: High-Speed Multiplexer

In this chapter, a second design example is presented. The considered circuit is a 16-to-1 multiplexer, optimized for high-speed operation. The circuit is designed in a 90 nm CMOS technology, and compared against a CMOS standard-cell implementation.

Design Example IV: Advanced Encryption Standard (AES)

In this chapter, a fourth design example is presented. The implemented circuit is the Advanced Encryption Standard (AES) which is another cryptographic block. In this implementation, the static power consumption of the MCML gates is reduced by applying the Power Gated MCML (PG-MCML) technique where the current source of the gates is switched off when there is no activity. The example block is implemented by using both MCML and CMOS gates. The power consumption, area, and the DPA-resistance figures with the one of static CMOS and conventional MCML are compared. The results show that the PG-MCML library can achieve a power consumption comparable with the one of static CMOS, thus proving that PG-MCML cells can suit the strict power budget of battery operated devices.

Design Example I: Low-Noise Encoder Circuit for A/D Converter

In the previous chapters, we have presented an analysis of MCML circuits and deducted design guidelines, specifically for standard cells. We have then presented a methodology for designing MCML standard-cell libraries and a design flow for implementing MCML standard-cell based circuits. In this chapter, we will present the implementation of an MCML standard-cell library in a 0.18 μm CMOS technology, and the RTL-to-GDSII design flow. We will then present the redesign in MCML of a CMOS standard-cell based decoder circuit for an analog-to-digital converter. As part of a mixed signal circuit, this design example targets low-noise operation.

Design Methodology for MCML Standard Cells

In the previous chapters, an analysis of MCML circuits was presented. In this chapter, issues specific to the application of a standard-cell methodology will be discussed. After introducing the standard-cell approach, methods for constructing optimum MCML logic gates will be presented. An approach to choose efficient functions for a standard-cell library will be proposed, built on the presented analysis framework. Finally, practical issues of standard-cell implementation will be discussed.

Design of MOS Current-Mode Logic Cells

A detailed analysis of basic MOS current-mode logic circuits has been presented in the previous chapter. Based on this model, in this chapter the design of MCML gates is discussed. Trade-offs are analyzed, and a design methodology is proposed. Then, the circuit-level implementation of specific cells is discussed, including sequential (latches, flip-flops) and tri-state circuits. Finally, some variants of the classical MCML style targeting higher speed or lower power are presented.

Self-heating effects on the thermal noise of deep sub-micron FD-SOI MOSFETs

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate lengths shrink and the power density values increase. In analog design, one of the main drawbacks of elevated temperature is the deterioration of the thermal noise performance. For observing the thermal noise performance of FD-SOI MOSFETs, a thermal model for the device self-heating is used. The influence of self-heating on the thermal noise is examined by activating and inactivating the self-heating thermal model and comparing the results. It is shown that self-heating can deteriorate the thermal noise current (up to 18%) and the input referred thermal noise voltage (up to 37%) significantly for short channel FD-SOI devices.