Can C. Özturan

Parallel structures and dynamic load balancing for adaptive finite element computation

Abstract An adaptive technique for a partial differential system automatically adjusts a computational mesh or varies the order of a numerical procedure to obtain a solution satisfying prescribed accuracy criteria in an optimal fashion. We describe data structures for distributed storage of finite element mesh data as well as software for mesh adaptation, load balancing, and solving compressible flow problems. Processor load imbalances are introduced at adaptive enrichment steps during the course of a parallel computation. To correct this, we have developed three dynamic load balancing procedures based, respectively, on load imbalance trees, moment of inertia, and octree traversal. Computational results on an IBM SP2 computer are presented for steady and transient solutions of the three-dimensional Euler equations of compressible flow.

Computer and Information Sciences - ISCIS 2005

Invited Speakers.- Keeping Viruses Under Control.- Online Auctions: Notes on Theory, Practice, and the Role of Agents.- Computer Networks.- A Unified Approach to Survivability of Connection-Oriented Networks.- SCTP Based Framework for Mobile Web Agent.- An Agent-Based Scheme for Efficient Multicast Application in Mobile Networks.- An Enhanced One Way Function Tree Rekey Protocol Based on Chinese Remainder Theorem.- Admission Control for Multicast Routing with Quality of Service in Ad Hoc Networks.- An Efficient On-line Job Admission Control Scheme to Guarantee Deadlines for QoS-Demanding Applications.- A Methodology of Resilient MPLS/VPN Path Management Under Multiple Link Failures.- Sensor and Satellite Networks.- Comparison of Hyper-DAG Based Task Mapping and Scheduling Heuristics for Wireless Sensor Networks.- A Markov-Based Model to Analyze the Temporal Evolution and Lifetime of a Sensor Network.- Power-Efficient Seamless Publishing and Subscribing in Wireless Sensor Networks.- Group-Oriented Channel Protection for Mobile Devices in Digital Multimedia Broadcasting.- IP Traffic Load Distribution in NGEO Broadband Satellite Networks - (Invited Paper).- Cross-Layer Management of Radio Resources in an Interactive DVB-RCS-Based Satellite Network-(Invited Paper).- Aggressive Back off Strategy in Congestion Management Algorithm for DBS-RCS - (Invited Paper).- TCP-Peach++: Enhancement of TCP-Peach+ for Satellite IP Networks with Asymmetrical Bandwidth and Persistent Fades-(Invited Paper).- Security and Cryptography.- Automatic Translation of Serial to Distributed Code Using CORBA Event Channels.- Fault Tolerant and Robust Mutual Exclusion Protocol for Synchronous Distributed Systems.- Exact Best-Case End-to-End Response Time Analysis for Hard Real-Time Distributed Systems.- A Formal Policy Specification Language for an 802.11 WLAN with Enhanced Security Network.- A Generic Policy-Conflict Handling Model.- A Truly Random Number Generator Based on a Continuous-Time Chaotic Oscillator for Applications in Cryptography.- A New Cryptanalytic Time-Memory Trade-Off for Stream Ciphers.- SVM Approach with a Genetic Algorithm for Network Intrusion Detection.- Performance Evaluation.- Modeling Access Control Lists with Discrete-Time Quasi Birth-Death Processes.- Stochastic Bounds on Partial Ordering: Application to Memory Overflows Due to Bursty Arrivals.- QoS Evaluation Method in Multimedia Applications Using a Fuzzy Genetic Rule-Based System.- Impact of Setup Message Processing and Optical Switch Configuration Times on the Performance of IP over Optical Burst Switching Networks.- Characterizing Gnutella Network Properties for Peer-to-Peer Network Simulation.- Computing Communities in Large Networks Using Random Walks.- Fame as an Effect of the Memory Size.- Keeping Viruses Under Control.- Distributed Evaluation Using Multi-agents.- Classification of Volatile Organic Compounds with Incremental SVMs and RBF Networks.- E-Commerce and Web Services.- Agent Based Dynamic Execution of BPEL Documents.- A Fair Multimedia Exchange Protocol.- A Pervasive Environment for Location-Aware and Semantic Matching Based Information Gathering.- A Web Service Platform for Web-Accessible Archaeological Databases.- A WSDL Extension for Performance-Enabled Description of Web Services.- A Novel Authorization Mechanism for Service-Oriented Virtual Organization.- Metrics, Methodology, and Tool for Performance-Considered Web Service Composition.- Brazilian Software Process Reference Model and Assessment Method.- Multiagent Systems.- A Secure Communication Framework for Mobile Agents.- A Novel Algorithm for the Coordination of Multiple Mobile Robots.- Multiagent Elite Search Strategy for Combinatorial Optimization Problems.- Managing Theories of Trust in Agent Based Systems.- Applying Semantic Capability Matching into Directory Service Structures of Multi Agent Systems.- Self-organizing Distribution of Agents over Hosts.- Machine Learning.- Evolutionary Design of Group Communication Schedules for Interconnection Networks.- Memetic Algorithms for Nurse Rostering.- Discretizing Continuous Attributes Using Information Theory.- System Identification Using Genetic Programming and Gene Expression Programming.- ARKAQ-Learning: Autonomous State Space Segmentation and Policy Generation.- Signature Verification Using Conic Section Function Neural Network.- Fusion of Rule-Based and Sample-Based Classifiers - Probabilistic Approach.- Construction of a Learning Automaton for Cycle Detection in Noisy Data Sequences.- Information Retrieval and Natural Language Processing.- A New Trend Heuristic Time-Variant Fuzzy Time Series Method for Forecasting Enrollments.- Using GARCH-GRNN Model to Forecast Financial Time Series.- Boosting Classifiers for Music Genre Classification.- Discriminating Biased Web Manipulations in Terms of Link Oriented Measures.- ORF-NT: An Object-Based Image Retrieval Framework Using Neighborhood Trees.- Text Categorization with Class-Based and Corpus-Based Keyword Selection.- Aligning Turkish and English Parallel Texts for Statistical Machine Translation.- The Effect of Windowing in Word Sense Disambiguation.- Pronunciation Disambiguation in Turkish.- Image and Speech Processing.- Acoustic Flow and Its Applications.- A DCOM-Based Turkish Speech Recognition System: TREN - Turkish Recognition ENgine.- Speaker Recognition in Unknown Mismatched Conditions Using Augmented PCA.- Real Time Isolated Turkish Sign Language Recognition from Video Using Hidden Markov Models with Global Features.- An Animation System for Fracturing of Rigid Objects.- 2D Shape Tracking Using Algebraic Curve Spaces.- A Multi-camera Vision System for Real-Time Tracking of Parcels Moving on a Conveyor Belt.- Selection and Extraction of Patch Descriptors for 3D Face Recognition.- Implementation of a Video Streaming System Using Scalable Extension of H.264.- Blotch Detection and Removal for Archive Video Restoration.- Performance Study of an Image Restoration Algorithm for Bursty Mobile Satellite Channels.- Algorithms and Database Systems.- Polymorphic Compression.- Efficient Adaptive Data Compression Using Fano Binary Search Trees.- Word-Based Fixed and Flexible List Compression.- Effective Early Termination Techniques for Text Similarity Join Operator.- Multimodal Video Database Modeling, Querying and Browsing.- Semantic Load Shedding for Prioritized Continuous Queries over Data Streams.- Probabilistic Point Queries over Network-Based Movements.- Effective Clustering by Iterative Approach.- Recursive Lists of Clusters: A Dynamic Data Structure for Range Queries in Metric Spaces.- Incremental Clustering Using a Core-Based Approach.- Indexing of Sequences of Sets for Efficient Exact and Similar Subsequence Matching.- An Investigation of the Course-Section Assignment Problem.- Crympix: Cryptographic Multiprecision Library.- Optimal Control for Real-Time Feedback Rate-Monotonic Schedulers.- Graphical User Interface Development on the Basis of Data Flows Specification.- Theory of Computing.- Generalizing Redundancy Elimination in Checking Sequences.- A Computable Version of Dinis Theorem for Topological Spaces.- Improved Simulation of Quantum Random Walks.- An Alternative Proof That Exact Inference Problem in Bayesian Belief Networks Is NP-Hard.- Recovering the Lattice of Repetitive Sub-functions.- Epilogue.- Erol Gelenbes Career and Contributions.

Load balancing for the parallel adaptive solution of partial differential equations

Abstract An adaptive technique for a partial differential system automatically adjusts a computational mesh or varies the order of a numerical procedure with a goal of obtaining a solution satisfying prescribed accuracy criteria in an optimal fashion. Processor load imbalances will, therefore, be introduced at adaptive enrichment steps during the course of a parallel computation. We develop and describe three procedures for retaining and restoring load balance that have low unit cost and are appropriate for use in an adaptive solution environment. Tiling balances load by using local optimality criteria within overlapping processor neighborhoods. Elemental data are migrated between processors within the same neighborhoods to restore balance. Tiling is restricted to uniform two-dimensional meshes and provides limited control of communications volume by priority-based element selection criteria. These shortcomings can potentially be overcome by creating a dynamic partition graph connecting processors and their neighboring regions. After coloring the edges of the graph, elemental data are iteratively transferred between processors by pairwise exchange to permit a more global migration. Octree decomposition of a spatial domain is a successful three-dimensional mesh generation strategy. The octree structure facilities a rapid load balancing procedure by performing tree traversals that (i) appraise subtree costs and (ii) partition spatial regions accordingly. Computational results are reported for two- and three-dimensional problems using nCUBE/2 hypercube, MasPar MP-2, and Thinking Machines CM-5 computers.

Fast custom instruction identification by convex subgraph enumeration

Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and silicon area combinations. This work introduces a novel method for adapting the instruction set to match an application captured in a high-level language. A simplified model is used to find the optimal instructions via enumeration of maximal convex subgraphs of application data flow graphs (DFGs). Our experiments involving a set of multimedia and cryptography benchmarks show that an order of magnitude performance improvement can be achieved using only a limited amount of hardware resources. In most cases, our algorithm takes less than a second to execute.

CHIPS: Custom Hardware Instruction Processor Synthesis

This paper describes an integer-linear-programming (ILP)-based system called custom hardware instruction processor synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.

Parallel automatic adaptive analysis

Abstract Consideration is given to the techniques required to support adaptive analysis of automatically generated unstructured meshes on distributed memory MIMD parallel computers. Emphasis is placed on the structures needed to support effective parallel computations when the numerical discretization, the mesh, is defined and evolves during the computation. The key base structures are a distributed mesh based on a topological hierarchy, and a parallel distributed octree. Parallel control of the mesh and octree structures is done through a set of partition communication operations and entity migration routines. Load balance is maintained through iterative load balance, or distributed repartitioning. Building on these structures, procedures to automatically generate and adaptively refine meshes in parallel, starting from CAD geometric models, are given. Finally, the combination of these techniques to produce a parallel automated analysis procedure is demonstrated.

Parallel three-dimensional mesh generation

Abstract This paper discusses the development of an automatic mesh generation technique designed to effectively operate on multiple instruction, multiple data (MIMD) parallel computers. The paper first provides an overview of a new octree-based procedure designed for the parallel generation of meshes of large numbers of elements directly from solid model representations. The techniques required to implement such a procedure using message passing on MIMD computers are emphasized. Technical issues considered include the region meshing algorithm, multiple octant migration and incremental load balancing.

Parallel adaptive mesh refinement and redistribution on distributed memory computers

Abstract A procedure to support parallel refinement and redistribution of two-dimensional unstructured finite element meshes on distributed memory computers is presented. The procedure uses the mesh topological entity hierarchy as the underlying data structures to easily support the required adjacency information. Mesh refinement is done by employing links back to the geometric representation to place new nodes on the boundary of the domain directly on the curved geometry. The refined mesh is then redistributed by an iterative heuristic based on the Leiss-Reddy [1] load balancing criteria. A fast parallel tree edge-coloring algorithm is used to pair processors having adjacent partitions and forming a tree structure as a result of Leiss-Reddy load request criteria. Excess elements are iteratively migrated from heavily loaded to less loaded processors until load balancing is achieved. The system is implemented on a massively parallel MasPar MP-1 system with a SIMD style of computation and uses message passing primitives to migrate elements during the mesh redistribution phase. Performance results of the redistribution heuristics on various test meshes are given.

Optimizing instruction-set extensible processors under data bandwidth constraints

The authors present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. The authors describe a scalable integer linear programming (ILP) formulation, that extracts the most profitable set of instruction-set extensions given the available data bandwidth and transfer latency. Unlike previous approaches, the authors differentiate between number of inputs and outputs for instruction-set extensions and the number of register file ports. This differentiation makes the approach applicable to architectures that include architecturally visible state registers and dedicated data transfer channels. The authors support a comprehensive design space exploration to characterize the area/performance trade-offs for various applications. The authors evaluate our approach using actual ASIC implementations to demonstrate that our automatically customized processors meet timing within the target silicon area. For an embedded processor with only two register read ports and one register write port, the authors obtain up to 4.3times speed-up with extensions incurring only a 35% area overhead

Parallel three-dimensional mesh generation on distributed memory MIMD computers

This paper discusses the development of an automatic mesh generation technique designed to operate effectively on multiple instruction multiple data (MIMD) parallel computers. The meshing approach is hierarchical, that is, model entities are meshed after their boundaries have been meshed. Focus is on the region meshing step. An octree is constructed to serve as a localization tool and for efficiency. The tree is also key to the efficient parallelization of the meshing process since it supports the distribution of load to processors. The parallel mesh generation procedure repartitions the domain to be meshed and applies on processor face removals until all face removals with local data have been performed. The portion of the domain to be meshed remaining is dynamically repartitioned at the octant level using an Inertial Recursive Bisection method and local face removals are reperformed. Migration of a terminal octant involves migration of the octant data and the octants mesh faces and/or mesh regions. Results show relatively good speed-ups for parallel face removals on small numbers of processors. Once the three-dimensional mesh has been generated, mesh regions may be scattered across processors. Therefore, a final dynamic repartitioning step is applied at the region level to produce a partition ready for finite element analysis.