Günhan Dündar

Computing Gradient Vector and Jacobian Matrix in Arbitrarily Connected Neural Networks

This paper describes a new algorithm with neuron-by-neuron computation methods for the gradient vector and the Jacobian matrix. The algorithm can handle networks with arbitrarily connected neurons. The training speed is comparable with the Levenberg-Marquardt algorithm, which is currently considered by many as the fastest algorithm for neural network training. More importantly, it is shown that the computation of the Jacobian, which is required for second-order algorithms, has a similar computation complexity as the computation of the gradient for first-order learning methods. This new algorithm is implemented in the newly developed software, Neural Network Trainer, which has unique capabilities of handling arbitrarily connected networks. These networks with connections across layers can be more efficient than commonly used multilayer perceptron networks.

An evolutionary approach to automatic synthesis of high-performance analog integrated circuits

This paper presents an analog integrated circuit synthesis system based on an evolutionary approach. The system contains several novel features. One of these is the high-performance optimization algorithm, which is a combination of evolutionary strategies and simulated annealing. Modeling of dc parameters is done via a fast dc simulator developed for this purpose whereas modeling of ac parameters can be done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. This way, the optimized circuit becomes tolerant to process variations. The synthesis system has been tested on several independent examples and synthesized circuits have been verified functionally with SPICE simulations. Finally, a prototype chip composed of the three examples has been manufactured. The measurement results have demonstrated the validity of the synthesis system on silicon.

The effects of quantization on multilayer neural networks

The effect of weight quantization in multilayer neural networks is discussed. A method is derived by which one can predict the performance degradation at the output given the properties of the network and number of bits of quantization. Predictions from this method are evaluated against simulation results. An algorithm to decrease the noise at the output is presented and the results are compared with those above.

An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined by finding the boundary values of the coefficient using linear programming. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware-efficient filters. The superiority of the algorithm on existing methods in terms of SPT term count, design time, hardware complexity, and power performance is shown with several design examples. Up to 30% reduction in the number of SPT terms is achieved over unoptimized Remez coefficients, which is 20% better than compared optimization methods. The average power saving is 20% over unoptimized coefficients, which is up to 14% better than optimized coefficients obtained with existing methods.

Fast custom instruction identification by convex subgraph enumeration

Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and silicon area combinations. This work introduces a novel method for adapting the instruction set to match an application captured in a high-level language. A simplified model is used to find the optimal instructions via enumeration of maximal convex subgraphs of application data flow graphs (DFGs). Our experiments involving a set of multimedia and cryptography benchmarks show that an order of magnitude performance improvement can be achieved using only a limited amount of hardware resources. In most cases, our algorithm takes less than a second to execute.

Analog Layout Generator for CMOS Circuits

In this paper, we present a new layout level automation tool for analog CMOS circuits, namely, analog layout generator (ALG). ALG is capable of generating individual or matched components as well as placement and routing. ALG takes performance considerations into account, optimizing the layout in each step. A distinguishing feature of the tool is primarily providing spectra of generation possibilities ranging from full custom to automatic generation. ALG is not only designed to work as a standalone tool but also implemented to be the final step of an analog automation flow. The flow supports circuit level specification in addition to layout level user specifications, so that it can be integrated into an analog automation system. Another feature of ALG is its interaction with a layout adviser tool, namely, YASA. YASA performs sensitivity simulations using a spicelike simulator providing sensitivities of performance parameters with respect to circuit parameters.

CHIPS: Custom Hardware Instruction Processor Synthesis

This paper describes an integer-linear-programming (ILP)-based system called custom hardware instruction processor synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.

Evolution-based design of neural fuzzy networks using self-adapting genetic parameters

In this paper, an evolution-based approach to design of neural fuzzy networks is presented. The proposed strategy optimizes the whole fuzzy system with minimum rule number according to given specifications, while training the network parameters. The approach relies on an optimization tool, which combines evolution strategies and simulated annealing algorithms in finding the global optimum solution. The optimization variables include membership function parameters and rule numbers which are combined with genetic parameters to create diversity in the search space due to self-adaptation. The optimization technique is independent of the topology under consideration and capable of handling any type of membership function. The algorithmic details of the optimization methodology are discussed in detail, and the generality of the approach is illustrated by different examples.

Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions

Recently, most DSP systems have used multirate signal processing techniques or transforms for reducing computational complexity without compromising the system quality. In these techniques, realizing each constant separately is a redundant process as some constants appear more than once, and increases area and power consumption of the system. This paper introduces the concept of handling all coefficients in the system at the same time. To do this, the two-term expressions of constants in a system for adder and shifter minimization is presented.

A novel design method for discrete time chaos based true random number generators

Discrete time chaos based true random number generators are lightweight cryptographic primitives that offer scalable performance for the emerging low power mobile applications. In this work, a novel design method for discrete time chaos based true random number generators is developed using skew tent map as a case study. Optimum parameter values yielding maximum randomness are calculated using a mathematical model of true random number generator. A practical information measure is used to determine the maximum allowable parameter variation limits. Appropriate mapping between dynamic system and circuit parameters is established and a current mode skew tent map circuit is designed to validate proposed method.