Cancio Monteiro

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single-rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic implementations in cryptographic system. The novelty of this work is that we evaluate the dynamic logic and differential logic for one-phase 2-inputs logic in adiabatic mode in SPICE simulation. We analyze the power consumption of logic circuit along 16 possible transitions of 2-inputs logic during one cycle. The power traces show that adiabatic differential logic families are masking the input logic values, because they consume constant power during pre-charge and evaluation phases that enables the circuit to resist against power analysis attacks. Based on our results, we deduce that adiabatic differential logic families are promising candidates for further development to obtain a far more robust secure logic for countermeasure against power analysis attacks in smart card.

Low power secure AES S-box using adiabatic logic circuit

Numerous works on advanced encryption standard (AES) S-box architecture have been done using composite field arithmetic in Galois field. However, to the best of our knowledge, less information is available on both a secure circuit and the low power consumption. In this work, we implement our previous proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using multi-stage positive polarity Reed-Muller (PPRM) representation over composite field technique. The logic sharing method for frequently same logic function usage in the combination logic is applied. Consequently, the low-complexity, high resistive and the low-power consumption are achieved. The results in this paper are obtained from the SPICE simulation with 0.18-μm 1.8-V standard CMOS technology at operating frequency of 1.25-70 MHz. Base on the logic speed, security performance and low-power requirement, we deduce that our proposed logic is applicable for contactless smart cards, RFID tags, and wireless sensors.

An LSI implementation of a bit-parallel cellular multiplier over GF(2 4 ) using secure charge-sharing symmetric adiabatic logic

This paper presents a measurement result of a bit-parallel multiplier over GF(24) using a secure dual-rail charge-sharing symmetric adiabatic logic. The output functionality and the supply current traces of the fabricated LSI chip are measured in order to analyze the correlation of the current-to-data dependency in respect to the given input signal transitions for resistance against power analysis attack. Furthermore, the verification of the output signals of the LSI chip is measured at dynamic power clock frequency from 0.5-5 MHz.

Low power secure CSSAL bit-parallel multiplier over GF(2 4 ) in 0.18μm CMOS technology

In this paper, we present the post layout simulation result of our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in comparison with the symmetric adiabatic logic, 2N-2N2P, and the TDPL in the bit-parallel cellular multiplier over GF(24). The transitional supply current and the power fluctuation of each logic style are compared in order to verify the logic ability for resistance against side-channel analysis attacks in cryptographic hardware implementation. The full custom layout is designed in cadence virtuoso IC6.1 with the chip size of 172×155 μm2, and the cyclical power consumption of 14 pJ at 12.5 MHz using 0.18 μm CMOS technology for the CSSAL multiplier has achieved, while TDPL has 183 × 173 μm2 of the chip size, and the power consumption is 122.6 pJ which is about nine times higher than the one of the CSSAL. The low-power adiabatic logics are also thoroughly investigated, and the comparative data demonstrate that the proposed CSSAL multiplier has similar performance on power reduction and resistive to thwart side channel analysis at low frequency application.

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

—The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(2 4). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m 2 , and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m 2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.