Toshikazu Sekine

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to V dd . It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic

This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and resembles behavior of static CMOS. As a result, the delay time of the 2PADCL is shorter than that of the conventional ADCL circuit in the second and subsequent stages. The structure of 2PADCL can be also directly derived from static CMOS logic circuits. From the simulation results, we show that the energy consumption of the 2PADCL circuit is lower than those of other diode based adiabatic logic circuits

Two phase clocked adiabatic static CMOS logic

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10–100 MHz respectively.

VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic

An adiabatic logic is a technique to design low power digital VLSIs. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4 x 4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 4 x 4-bit 2PADCL multiplier was also 5.19mW at the 1.5 V DC power supply voltage.

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Abstract Side-channel attacks by cryptanalysis are becoming a serious threat for cryptographers, who are designing systems that are more robust in terms of hardware and algorithm threats, aiming to thwart violations of the secrecy of securely processed information. As our contribution on a related issue, we propose a new secure logic, called charge-sharing symmetric adiabatic logic (CSSAL), for resistance against differential power analysis (DPA) attacks. We verify the security of the proposed CSSAL by carefully analyzing the individual logic functions corresponding to 16 possible dual-input transitions. Then, we compare the results with those of previous secure logic styles using the same parameters and under the same conditions. The figure of merit to measure the resistance of the logic against DPA attacks has been calculated from the variation in power consumption per input transition. The SPICE simulation results show that our proposed logic balances the peak current traces for all input logic transitions, consuming power uniformly over every cycle, and thus making the input–output data resilient to a DPA attack. Moreover, the ability of the proposed CSSAL in a bit-parallel cellular multiplier over GF ( 2 m ) shows its significant power reduction compared to conventional secure logic styles and its efficient resistance to DPA attacks.

LSI implementation of a low-power 4 × 4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development-of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12MHz, a 4x4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4x4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4x4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 µm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4×4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single-rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic implementations in cryptographic system. The novelty of this work is that we evaluate the dynamic logic and differential logic for one-phase 2-inputs logic in adiabatic mode in SPICE simulation. We analyze the power consumption of logic circuit along 16 possible transitions of 2-inputs logic during one cycle. The power traces show that adiabatic differential logic families are masking the input logic values, because they consume constant power during pre-charge and evaluation phases that enables the circuit to resist against power analysis attacks. Based on our results, we deduce that adiabatic differential logic families are promising candidates for further development to obtain a far more robust secure logic for countermeasure against power analysis attacks in smart card.

Fundamental logics based on two phase clocked adiabatic static CMOS logic

This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 µm CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. From the simulation results, we find that 2PASCL inverter logic can save up to 97% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 10 to 100 MHz. Further, the power dissipation is the lowest when compared with other proposed simple adiabatic logic inverters. 2PASCL also achieves the highest fan-out performance. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.