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Featured researches published by Cao Li.


electronic components and technology conference | 2012

Application specific LED packaging for automotive forward-lighting application and design of whole lamp module

Fei Chen; Kai Wang; Zhangming Mao; Xing Fu; Cao Li; Mengxiong Zhao; Sheng Liu

In this study, we first analyse the requirements both in optical and thermal aspects in theory. With the results of theoretical analysis, we design the application specific light emitting diode (LED) packaging (ASLP) with optimized structural parameters and choose appropriate packaging materials. According to this design, several samples are made and tested. The test results show that the LED packaging can provide a light flux of 1100 lm with a sharp cut-off and the chromaticity of packaging can comply with ECE regulations. In addition, the thermal resistance of packaging can be less than 1.3 K/W when equivalent heat transfer coefficient of cooling system is about 5000 W/(m2·K). Secondly, based on the test results, we design a supporting optical system with a novel freeform multi-reflector, an effective cooling system and even a whole headlamp module including low-beam and high-beam functions. Finally, we test the performances of the headlamp, and the test results in simulation can fully comply with ECE and GB regulations.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2015

21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding

Cao Li; Xuefang Wang; Shao Song; Sheng Liu

A 3-D chip-to-chip stacking technology is presented, in which several key techniques involving the wafer thinning process are integrated, through silicon via (TSV) etching and plating, redistribution layer formulation, and the flip chip chip bonding process. Nanoporous Cu-Sn microbump bonding technology is introduced, and a novel 3-D module-to-module bonding method is developed. Compared with the reported 3-D packaging technologies, a chip stacking module with more than 21 layers is obtained in the flip-chip stacking style. Each layer of the stacking module has an ultrathin thickness of 60-80 μm, and the pitch of the TSV is 200 μm. Such as bonding strength measurement, thermal cycling test and electrical measurement are implemented to evaluate the reliability of the chip stacking module. The results have shown that the presented 21-layer stacking module has a better tensile and shear strength, and preferable contact resistance, as well as over 1000 thermal cycles.


electronic components and technology conference | 2013

Novel design and reliability assessment of a 3D DRAM stacking based on Cu-Sn micro-bump bonding and TSV interconnection technology

Cao Li; Xuefang Wang; Mingxiang Chen; Shengjun Zhou; Yaping Lv; Sheng Liu

In this paper, FEA model of Cu-Sn micro-bump bonding module and Cu-Sn micro-bump/BCB adhesive hybrid bonding module subjected to thermal cycling are built respectively. Two types of double-chip-stacking module, with and without BCB, are prepared. Followed by a thermal cycling test, during which mechanical and electrical test are also implemented to assess the reliability of the bonded micro-bumps. It is found that with the increase of cycle number or temperature gap, samples fabricated by pure micro-bump bonding, rather than micro-bump/adhesive hybrid bonding, demonstrate a better performance in reliability. Similar conclusion has been arrived from simulation results. Although BCB is beneficial in promoting chip level bonding strength, areas nearby micro-bumps become more risky. As a solution, a novel stacking scheme is designed to improve chip level bonding strength and avoid micro bump reliability loss at the same time. In this process, Cu-Sn micro-bump bonding, with special surface structure on chips instead of BCB adhesive, is adopted to enhance the chip bonding strength. And by this stacking scheme, multiple-chip-stacking module with single layer thinned to 50 microns are fabricated successfully. In reliability test, the stacked module performs well both in terms of chip level bonding strength and micro interconnect reliability. Finally, a 11-layer stacked chip module has been successfully fabricated.


international conference on electronic packaging technology | 2012

Design of one novel LED airport runway centerline light suitable for various applications

Chuangang Ji; Mengxiong Zhao; Tao Peng; Fei Wang; Cao Li; Sheng Liu

Compared with traditional aviation ground runway lights, such as halogen lamps with low optical efficiency and poor color rendering index, LED have superior performance and begins to replace the halogen lamps to become the main aviation ground lamps. For aviation ground midline light require yellow or green light, we can choose a type of green or yellow LED to substitute the halogen lamps to achieve specific color light with high luminance and low power consumption for no color filtering from white light. The light intensity of midline lamps specified by National Transportation Safety Board cannot be satisfied by usual LED lamps. A new aviation ground taxiway midline light is made with freeform lens and new mechanical structure called angle adjustment plate. By our simulation, the new aviation ground taxiway midline light can be applied in different light intensity distribution requirement circumstance of aviation ground midline lighting.


international conference on electronic packaging technology | 2012

An innovative way to improve the reliability of gold wire in lighting emitting diodes (LEDs)

Run Chen; Xiang Gao; Xiaogang Liu; Cao Li; Sheng Liu

As the most promising candidate for the realization of high-efficiency light sources for general lighting, the high power lighting emitting diodes (LEDs) still have reliability issues that hinder the large scale application of LED devices. Nowadays, the reliability is becoming an essential barrier for LED devices to substitute the traditional light sources. Before it is applied into mass production, many kinds of experiments under harsh conditions should be done to predict its reliability. Among those factors affecting LEDs reliability, fractures in the gold wire cannot be underestimated. Gold wire is often used for providing an electrical interconnection with outside power, while after some typical package reliability tests, such as the thermal cycling and thermal shock tests [3], there are fractures at two critical zones, the second bond and neck of the first bond. It is confirmed that the failure is mainly caused by the coefficient of thermal expansion (CTE) mismatch between gold and other materials and the large deformation of the silicone enclosing the gold wire.


electronics packaging technology conference | 2011

Design of LED packaging module for automotive forward-lighting application

Fei Chen; Kai Wang; Mengxiong Zhao; Zhangming Mao; Jiawei Yao; Cao Li; Sheng Liu

In this study, we firstly analyse the requirements both in optical and thermal fields in theory. With the results of theoretical analysis, we design the application specific light emitting diode (LED) packaging (ASLP) with optimized structure parameters and appropriate packaging materials. According to this design, several samples are made and tested. The test results show that the LED packaging can provide a light flux of 1000lm with a sharp cut-off and the chromaticity of packaging can comply with ECE regulations. Also, the thermal resistance of packaging can be less than 1.3K/W when equivalent heat transfer coefficient of cooling system is about 5000 W/(m2·K). Secondly, based on the test results, we design a supporting optical system with a novel freeform multi-reflector, an effective cooling system and even a complete LED packaging module for automotive forward-lighting application, including low-beam and high-beam functions. Finally, we test the performances of the LED packaging module, and the test results in simulation can fully comply with ECE and GB regulations.


electronic components and technology conference | 2015

Modeling and simulation for the thermo -mechanical interfacial reliability of throug h-silicon-via for 3D IC integration

Hao Jiang; Gang Cao; Zhang Luo; Cao Li; Guoping Wang; Sheng Liu

To meet the needs of the continual scaling of wiring structures, 3D IC integration with through-silicon-vias has become the most important direction to go for further miniaturization. Compared to the conventional packaging, 3D integration based on the TSV technology has several inherent advantages, such as small size, high density and short interconnect path. Consequently, TSV technology has attracted wide spread interest in the circuits and devices, packaging and testing communities in the world. As the heart and key technology for 3D integration, TSV structures should be sufficiently reliable to guarantee the performance of the packaged devices. Among all the concerned reliability problems, thermo-mechanical interfacial reliability is crucial one which should deserve more attention. In this paper, modeling and simulation has been carried out to examine the impact of the thermal stress on the interfacial reliability of the TSV structures. Firstly, distribution of the thermal stresses and strains of the structure and the interface has been calculated by a thermo-mechanical FEA model. To obtain more appropriate results, the copper filled in the vias was considered to be elastic-plastic. The mechanical elastic property and the coefficients of thermal expansion (CTE) of copper and silicon were considered to be temperature dependent. Subsequently, a damage model was built up to simulate the initiation and propagation of the interfacial crack. Cohesive elements with “traction-separation” response were used in the model. Furthermore, energy release rate associated with interfacial crack growth was calculated and J-integral method for calculation of energy release rate was introduced to investigate the crack growth stability of TSV structures with preexisting cracks. Cases with cracks at different locations and various crack lengths have been simulated. Results indicate that thermal stress may concentrate on the interface with different materials. The stress concentration locations were the potential positions where the crack may be most likely initiated. And the simulation results of the damage model show that the interface crack growth may be unstable and cracks may initiate and propagate as the temperature difference is up to 325°C. And the interface may fail to work rapidly once it is damaged. For the preexisting cracks in the interface, they may propagate if the crack length is long enough. The estimated critical length of notch crack is about 2μm, and 4μm for buried cracks when a temperature difference 255 °C is applied on the structure. The energy release rate increases with the crack length. The results further show that the strain energy release rate for notch cracks is higher than the buried ones with the same crack length so that the notch cracks should deserve more attention during the manufacture processes.


electronic components and technology conference | 2013

Drop impact simulation and experimental validation on high power light emitting diodes modules

Cao Li; Tao Peng; Xuefang Wang; Mingxiang Chen; Sheng Liu

Impact behaviors of high-power LED are essential due to the possible poor adhesion of interfaces and should be studied. In this study, the analysis of dynamic response for high-power LED module under impact load is conducted with simplified theoretical analysis, experimental testing and numerical simulation. A self-made microelectronics drop impact tester is established. Then reliability performances of high power LED module subjected to drop test conditions are evaluated experimentally. Good reproducibility dynamic parameters of impact force-time, acceleration-time are recorded for evaluating the impact response through the signal processing. In addition, a theoretical analysis of the impact dynamic progress is conduced, which shows the self-made drop tester is relatively precise by comparing the theoretical and experimental results. The major failure modes of LED module include lens fall off and crack formation in the impact experiment. The numerical simulation is conducted by nonlinear FEA software ABAQUS for high-power LED drop impact process under different drop angle conditions. Because the drop impact is a transient dynamic process, the constitutive relations of solder material under high strain rate are taken into consideration. The purpose of numerical simulation is to obtain the distribution of local stress and deformation under drop impact process, which is significant for comprehensive and in-depth understanding for high-power LED module drop impact response.


international conference on electronic packaging technology | 2012

Dimension optimization of through silicon via(TSV) through simulation and design of experiment (DOE)

Xiang Gao; Run Chen; Cao Li; Sheng Liu


Archive | 2012

Alternating current frequency conversion speed regulation control box for coal mine underground coal mining machine

Guoshu Pu; Run Chen; Zhaohui Chen; Xiaogang Liu; Cao Li

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Sheng Liu

Huazhong University of Science and Technology

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Run Chen

Huazhong University of Science and Technology

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Xiaogang Liu

Huazhong University of Science and Technology

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Mengxiong Zhao

Huazhong University of Science and Technology

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Xuefang Wang

Huazhong University of Science and Technology

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Fei Chen

Huazhong University of Science and Technology

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Mingxiang Chen

Huazhong University of Science and Technology

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Tao Peng

Huazhong University of Science and Technology

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Xiang Gao

Huazhong University of Science and Technology

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Zhangming Mao

Huazhong University of Science and Technology

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