Carl A. Bender
IBM
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Publication
Featured researches published by Carl A. Bender.
Ibm Systems Journal | 1995
Craig B. Stunkel; Dennis G. Shea; B. Aball; M. G. Atkins; Carl A. Bender; D. G. Grice; Peter H. Hochschild; Douglas J. Joseph; Ben J. Nathanson; R. Swetz; R. F. Stucke; M. Tsao; P.R. Varker
The heart of an IBM SP2™ system is the HighPerformance Switch, which is a low-latency, highbandwidth switching network that binds together RISC System/6000® processors. The switch incorporates a unique combination of topology and architectural features to scale aggregate bandwidth, enhance reliability, and simplify cabling. It is a bidirectional multistage interconnect subsystem driven by a common oscillator, and delivers both data and service packets over the same links. Switching elements contain a dynamically allocated shared buffer for storing blocked packet flits. The switch is constructed primarily from switching elements (the Vulcan switch chip) and adapters (the SP2 communication adapter). The SP2 communication adapter uses a variety of techniques to improve bandwidth and offload communication tasks from the node processor. This paper examines the switch architecture and presents an overview of its support software.
Ibm Journal of Research and Development | 2008
Carl A. Bender; Pia N. Sanda; Prabhakar Kudva; Ricardo Mata; Vikas Pokala; Ryan Haraden; Matthew Schallhorn
The soft-error resilience of the IBM POWER6™ processor I/O (input/output) subsystem was measured using proton beam irradiation to accelerate the effect of single-event upsets. Test programs exercised each of the adapters on the chip. Error rates were measured for various cases ranging from idle to high I/O bandwidth and utilization. The POWER6 processor and I/O hub subsystem work together to maintain resiliency even under strenuous irradiation conditions.
ieee international conference on high performance computing data and analytics | 2004
Rama K. Govindaraju; Peter H. Hochschild; Don Grice; Kevin J. Gildea; Robert S. Blackmore; Carl A. Bender; Chulho Kim; Piyush Chaudhary; Jason E. Goscinski; Jay R. Herring; Steven Martin; John S. Houston
In this paper we describe the architecture, design, and performance of the new cluster switch fabric and adapter called HPS (High Performance Switch). HPS delivers very low latency and very high bandwidth. We demonstrate latency of less than 4.3us MPI library; 1.8GB/s of delivered unidirectional bandwidth and 2.9GB/s of bidirectional bandwidth between 2 MPI tasks running on 1.9GHz Power 4+ IH based nodes. HPS also supports RDMA (remote direct memory access capability). A unique capability of RDMA over HPS is that reliable RDMA is supported over an underlying unreliable transport (unlike Infiniband and other RDMA transport protocols which depend on the underlying transport being reliable). We profile the performance of RDMA and its impact on striping for systems in which multiple network adapters are available to tasks of parallel jobs.
Archive | 1997
Kathy Sue Barkey; Carl A. Bender; Derrick Leroy Garmire; Harold Edgar Roman; Daniel Gerard Smyth
Archive | 1997
Carl A. Bender; Paul David Dinicola; Kevin J. Gildea; Rama K. Govindaraju; Chulho Kim; Jamshed H. Mirza; Gautam H. Shah; Jaroslaw Nieplocha
Archive | 1997
Kathy Sue Barkey; Carl A. Bender; Derrick Leroy Garmire; Harold Edgar Roman; Daniel Gerard Smyth
Archive | 1997
Carl A. Bender; Paul David Dinicola; Kevin J. Gildea; Rama K. Govindaraju; Chulho Kim; Jamshed H. Mirza; Gautam H. Shah
Archive | 1993
Christine M. Desnoyers; Derrick Leroy Garmire; Sheryl Marie Genco; Donald G. Grice; William Robert Milani; Michael Patrick Muhlada; Donna Carol Myers; Peter K. Szwed; Vadim Miron Tsinker; Antoinette Elaine Vallone; Carl A. Bender
Archive | 2003
Carl A. Bender; Walker B. Carroll; Nilesh M. Dange; John S. Houston; Douglas J. Joseph
Archive | 2006
Carl A. Bender; Patrick Allen Buckland; Steven Mark Thurber; Adalberto Guillermo Yanes